3886 datasheet(287/380 Pages) RENESAS

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3886 Group User’s Manual

APPLICATION

2.15 Flash memory

(2)

Control example in CPU reprogramming mode

In this example, the built-in flash memory is reprogrammed in the CPU reprogramming mode by

serial I/O, receiving the reprogramming data (updated data).

Figure 2.15.9 shows an example of the reprogramming system for the built-in flash memory in the

CPU reprogramming mode.

Fig. 2.15.9 Example of reprogramming system for built-in flash memory in CPU reprogramming

mode

q Specifications

➀ CPU reprogramming mode is selected/released by the input signal to Pi2.

➁ Updated data is received by serial I/O.

➂ The transfer enable state of serial transmit side is judged by “L” level input to Pi0.

➃ VPP control circuit is turned ON/OFF by the output from Pi1 (refer to Figure 2.15.14 and Figure

2.15.15).

VPP circuit control port

M38869FF

VPP(CNVSS)

XIN XOUT

Pi2

User reset signal

VPP *

control

circuit

Pi1

10 MHz

CLK1

RxD1

TxD1

Pi0

Port for CPU reprogramming mode

switch

(CPU reprogramming mode is

selected/released by port Pi2 input signal)

VCC

VSS

RESET

(i = 0 to 8)

Reprogramming data input control

(Updated data is received by serial I/O)

Refer to Figure 2.15.14 and Figure 2.15.15.

ON/OFF of VPP control

circuit is controlled by

port Pi1 output.

12V

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