3886 datasheet(288/380 Pages) RENESAS

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3886 Group User’s Manual

APPLICATION

2-171

2.15 Flash memory

Fig. 2.15.10 CPU reprogramming control program example (1)

*1: Waiting by software until VPP input voltage is stabilized at VPPH

is recommended. (Refer to Figures 2.15.14 and 2.15.15 VPP voltage control timing A .)

*2: The waiting time depends on VPP control circuit (Refer to Figures

2.15.14 and 2.15.15 VPP voltage control timing C .)

CPU reprogramming mode

select bit = “1”

Port Pi1 = “1”

Interrupt disable processing

YES

Wait 5 ms

CPU reprogramming

mode monitor flag

= “1” ?

YES

CPU reprogramming

control program example

Serial I/O initialization

set

Note: In this example, the following program is transferred to and executed on the internal

RAM.

Apply VPP voltage = VPPH

waiting for stabilization *1

CPU reprogramming

mode monitor flag

= “1” ?

In this program example, the flash memory is reprogrammed by

receiving each 1 byte of data from serial I/O.

12 V applied circuit

to VPP “ON”

➁ Transition to CPU reprogramming mode

Initialize watchdog timer (write to

watchdog timer control register) to prevent

generation of watchdog timer interrupt

during this processing.

Confirmation that CPU

reprogramming mode

is valid.

Continued to “CPU reprogramming control

program example (2)” on the next page.

➀ Preparing for transition to CPU

reprogramming mode

Disable the interrupt of built-in

peripheral functions in this processing.

Also, initialize watchdog timer (write to

watchdog timer control register) to

prevent generation of watchdog timer

interrupt.

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