7480 datasheet(155/337 Pages) RENESAS

155 / 337 page

7480 Group and 7481 Group User's Manual

1-138

HARDWARE

1.14.4 Bus Arbitration

In the serial I/O communications of the contention

bus system shown in Figure 1.14.23, transmit data

may not correctly be sent on the transmission line

because of bus collision.

In the 7480 Group and 7481 Group, if the comparison

of the level of serial I/O transmit pin TxD with that

of serial I/O receive pin RxD results in a mismatch,

the bus arbitration interrupt request is generated.

This indicates that the bus collision occurred.

When the bus collision detection enable bit of the

bus collision detection control register is set to ‘1’,

bus collision detection can be performed. In addition,

bus collision detection is valid when any of the

following conditions is selected:

Serial I/O mode

• Clock synchronous serial I/O

• Clock asynchronous serial I/O (UART)

Synchronous clock

• BRG output divided

• External clock (or external clock/16)

Figure 1.14.23 Contention bus system communications

1.14 Serial I/O

(1)

Block Diagram

Figure 1.14.24 shows the block diagram of the bus arbitration interrupt.

Figure 1.14.24 Block Diagram of Bus Arbitration Interrupt

TxD pin

RxD pin

Synchronous clock

Bus collision detection enable bit

Transmit enable bit

Bus arbitration interrupt request

TxD

RxD

Interface

Driver/

Receiver

7480 Group

7481Group

LAN data bus

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