7480 datasheet(186/337 Pages) RENESAS

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7480 Group and 7481 Group User's Manual

1-169

1.19 Power Saving Function

HARDWARE

(2)

Transition to Wait Mode

The transition from the normal mode to the wait mode is described below.

Recovery from Wait Mode by Reset Input

Execute the WIT instruction while the WIT instruction is valid.

Recovery from Wait Mode by Accepting Interrupt Request

Execute the WIT instruction while the WIT instruction is valid after the interrupt for terminating the

wait mode is set.

For the setting of the valid/invalid of the WIT instruction, refer to Section 1.19.4 Setting of Valid/

Invalid of STP and WIT Instructions.

1.19.4 Setting of Valid/Invalid of STP and WIT Instructions

In the 7480 Group and 7481 Group, the valid/invalid of the STP and WIT instructions can be selected with

the STP instruction operation control register. The STP and the WIT instruction are invalid after the system

is released from reset to prevent the program from a runaway.

Writing twice successively to the STP instruction operation control register makes the STP and the WIT

instruction valid, while non-successive writing to the register (for example, a single write) makes these

instructions invalid. As the STP and the WIT instruction remain invalid after the system is released from

reset, successive writing is used to prevent the clock oscillation from stopping due to erroneous data

written during a program runaway.

Figure 1.19.7 shows the setting of valid/invalid of the STP and WIT instructions.

Figure 1.19.7 Setting of Valid/Invalid of STP and WIT Instructions

Procedure 1 Setting interrupt disable flag of processor status register to ‘1’ (interrupt disabled)

STP and WIT instructions invalid

Procedure 2 Setting STP instruction operation control register (twice successive writing) (Note 1)

STP instruction operation control register (STPCON) [Address 00DE16]

1. A write of ‘1’

STP and WIT valid/Invalid selection

0: Valid

1: Invalid

STP instruction operation control register (STPCON) [Address 00DE16]

2. Selection of valid/invalid of STP and WIT instructions (Note 2)

Notes 1: A single write to the STP instruction operation control register makes the STP

and WIT instructions invalid.

2: If invalidating the STP and WIT instructions, the second write can be omitted.

Procedure 3 Clearing interrupt disable flag of processor status register to ‘0’ (interrupt enabled)

when using interrupts.

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