| Electronic Components Datasheet Search |
|
ST7637 Datasheet(PDF) 181 Page - Sitronix Technology Co., Ltd. |
|
|
|||||||||||||||||||||||||||||
ST7637 Datasheet(HTML) 181 Page - Sitronix Technology Co., Ltd. |
|
181 / 210 page ![]() ST7637 Ver 1.6 181/210 2009/03 (VDD=1.8V, Ta= 25°C, die) Rating Item Signal Symbol Condition Min. Max. Units Address hold time tAH8 15 — Address setup time A0 tAW8 15 — System cycle time (WRITE) tCYC8 260 — ns /WR L pulse width (WRITE) tCCLW 80 — /WR H pulse width (WRITE) WR tCCHW 170 — System cycle time (READ) tCYC8 110 — /RD L pulse width (READ) tCCLR 70 — /RD H pulse width (READ) RD (ID) tCCHR When read ID data 25 — System cycle time (READ) tCYC8 450 — /RD L pulse width (READ) tCCLR 140 — /RD H pulse width (READ) RD (FM) tCCHR When read from frame memory 300 — WRITE data setup time tDS8 60 — WRITE data hold time tDH8 10 — READ access time (ID) tACC8 (ID) — 60 READ access time (FM) tACC8 (FM) CL = 30 pF — 90 READ Output disable time D0 to D7 tOH8 CL = 30 pF — 80 ns *1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tCYC8 ℃ – tCCLW – tCCHW) for (tr + tf) (tCYC8 ℃ – tCCLR – tCCHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tCCLW and tCCLR are specified as the overlap between /CS being “L” and WR and RD being at the “L” level. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |