ST7787 datasheet(173/217 Pages) SITRONIX

173 / 217 page

ST7787

Ver. 1.7

2008.04.18

173

10.2.7 DISSET5 (B6h): Display Function set 5

B6H

DISSET (Display Function set 5)

Inst / Para

D/CX

WRX

RDX

D17-8

(Code)

DISSET5

↑

(B6h)

st Parameterr

↑

---

NO1

NO0

STD1

STD0

EQ1

EQ0

02h

nd Paramete

↑

---

PTG1

PTG0

PT1

PT0

02h

NOTE: “-“ Don’t care

Description

-1st parameter: Set output waveform relation.

-NO[1:0]: Set the amount of non-overlap of the gate output

NO[1:0]

Amount of non-overlap of the gate output

Refer the Internal oscillator

Refer the PCLK

2 clock cycle

8 clock cycle

4 clock cycle

16 clock cycle

8 clock cycle

32 clock cycle

10 clock cycle

40 clock cycle

-SDT[1:0]: Set delay amount from gate signal falling edge of the source output.

SDT[1:0]

Amount of non-overlap of the gate output

Refer the Internal oscillator

Refer the PCLK

1 clock cycle

4 clock cycle

2 clock cycle

8 clock cycle

3 clock cycle

12 clock cycle

4 clock cycle

16 clock cycle

-EQ[1:0]: Set the Equalizing period

-2nd parameter: Set the output waveform in non-display area.

-PTG[1:0]: Determine gate output in a non-display area in the partial mode

-PT[1:0]: Determine Source /VCOM output in a non-display area in the partial mode

EQ[1:0]

Amount of non-overlap of the gate output

Refer the Internal oscillator

Refer the PCLK

0 clock cycle

4 clock cycle

16 clock cycle

6 clock cycle

24 clock cycle

8 clock cycle

32 clock cycle

PTG[1:0]

Gate output in a non-display area

Normal scan

Fix on VGL

Source output on non-display area

VCOM output on non-display area

PT[1:0]

Positive

Negative

Positive

Negative

V63

VCOML

VCOMH

V63

VCOML

VCOMH

AGND

Hi-z

AGND

Restriction

-If this register not using the register need be reserved.

Gate Non-overlap period

Gn+1

VCOM

Delay

time

for

source

output

EQ period

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