TMPR28051 datasheet(83/90 Pages) AGERE

83 / 90 page

Data Sheet

August 1999

TMPR28051 STS-1/AU-3 (STM-0) Mapper

Lucent Technologies Inc.

Timing Characteristics (continued)

Operational Timing (continued)

The output clock specifications are shown in Table 40.

* The duty-cycle distortion added to the TSTS1CLKOUT signal is

≤2% worst case when measured from 1.5 V in to 1.5 V out with a 2 ns rise

time input.

Table 41 lists the propagation delay (tPD) specifications for the output signals. The digital system interface timing is

shown in Figure 11, page 68.

* Propagation delay skew, tPLH—tPHL, is ±200 ps.

Notes:

↑ represents a low-to-high transition.

↓ represents a high-to-low transition.

Table 40. Output Clock Specifications

Signal Name

Frequency

Test

Conditions

Rise Time

Fall Time

Unit

Min

Max

Min

Max

TCLK[1:28]

(DS1 Mode)

1.544 MHz ± 5%

CL = 50 pF

—

TCLK[1:28]

(E1 Mode)

2.048 MHz ± 5%

CL = 50 pF

—

TSTS1CLKOUT*

51.84 MHz ± 5%

CL = 15 pF

—

19.44 MHz ± 5%

CL = 15 pF

—

6.48 MHz ± 5%

CL = 15 pF

—

Table 41. Output Timing Specifications

Output Name

Reference CLK

Test

Conditions

Propagation Delay *

Unit

tPD

Min

Max

Transmit Signals

TDATA[28:1]

TCLK[1:28]

↑↓

CL = 25 pF

190

TSTS1DATA[7:0]

TSTS1CLKIN

↑

CL = 15 pF

TSTS1PAR

TSTS1CLKIN

↑

CL = 15 pF

TSTS1DATA7

TSTS1CLKIN

↑

CL = 15 pF

3.5

JTAG Signal

TDO

TCK

↓

CL = 50 pF

1.5

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