TMPR28051 datasheet(60/90 Pages) AGERE

60 / 90 page

Data Sheet

TMPR28051 STS-1/AU-3 (STM-0) Mapper

August 1999

Lucent Technologies Inc.

Microprocessor Interface Description (continued)

Table 15. Registers 0x00—0x16: Device-Level Control, Alarm, and Mask Bits (continued)

Address

(Hex)

Bit #

Name

Function

Reset

Default

(Hex)

0x13

7—4

—

Reserved.

0x00

S1INS-3

The S1INS-[3:0] bits in register 0x13 are used to set the

four least significant bits of the S1 path overhead byte.

2S1INS-2

1S1INS-1

0S1INS-0

0x14

The bits in register 0x14 are for the S1 path overhead byte.

0x30

S1#DET-3

The S1#DET-[3:0] bits are used to set the number of con-

secutive, consistent values required by the receive S1 byte

before updating the value. Valid values for these registers

range from 3 to 15. Any value less than 3 defaults to 2

inside the device.

6S1#DET-2

5S1#DET-1

4S1#DET-0

S1-3

The S1-[3:0] bits are used to report the four least significant

bits of the S1 path overhead byte.

2S1-2

1S1-1

0S1-0

0x15

7—0

DEVID-[7:0]

DEVID-[7:0] bits in register 0x15 are used to report the

device ID.

0x51

0x16

—

The DEVVER-[3:0] bits in register 0x16 are used to report

the device version. Anytime there are silicon changes that

modify the operation of this device, this register will be

incremented by 1.

Notes:

The reset default value is the device version.

Bits 7—4 are reserved.

—

7—4

—

DEVVER-3

DEVVER-2

DEVVER-1

DEVVER-0

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