TMPR28051 datasheet(5/90 Pages) AGERE

5 / 90 page

Advisory, Rev. 2

TMPR28051 STS-1/AU-3 (STM-0) Mapper

August 5, 1999

Device Advisory for Version 2 of the Device

Lucent Technologies Inc.

VT Mapping (VT) (continued)

VT-5. C-Bit Decoding

In the presence of a receive SONET/SDH bit error rate, the device may destuff the DS1 from the VT1.5 incorrectly.

This is the result of an error in the VT1.5 C-bit decoding process. The C-bit decoding process should be capable of

correcting single errors to the C bits. Because of this error, an error in the first or second C bit for position 2 will be

incorrectly decoded if the first C-bit position is calling for a stuff and the second C-bit position is not. The end result

of this error is that both positions will call for a stuff, resultin g in a bit being removed from the DS1 data stream. This

will force downstream equipment to experience a reframe.

The minimum time to false decode severity is as shown in Table VT-5 (in terms of seconds to false decode).

Table VT-5. Minimum Time (in Seconds) to

False Decode Severity of the C Bit

In the absence of an external bit error rate, the algorithm decodes these C bits correctly.

Test Pattern (TP) Generator/Monitor

TP-1. Test Pattern Insert

The transmitted test pattern comes out on the opposite edge with respect to the jitter-attenuated data.

TP-2. Test Pattern Drop

The test pattern detector always inverts the clock coming into the block before retiming the data.

Jitter Attenuation (JA)

JA-1. Jitter Attenuator

The digital jitter attenuator buffers are not functional. The DJACTL bit in register 0x01 should be set to 0 in this

device. Putting the device in the jitter attenuator mode (DJACTL = 1) causes loss of transmission.

BER

Theoretical

Actual

–3

125

0.25

10–4

12500

2.5

10–5

1250000

–6

1.25e+8

250

10–7

1.25e+10

2500

10–8

1.25e+12

2.5e+4

10–9

1.25e+14

2.5e+5

–10

1.25e+16

2.5e+6

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