TMPR28051 datasheet(37/90 Pages) AGERE

37 / 90 page

Data Sheet

August 1999

TMPR28051 STS-1/AU-3 (STM-0) Mapper

Lucent Technologies Inc.

Microprocessor Interface Description (continued)

The register bank architecture of the microprocessor interface is shown in Table 14. All addresses referred to in

this section are given in hexadecimal and binary notation, where hexadecimal is the left column and binary is the

right column under Address.

Note: Bits in registers 0xC0—0xFF can have one of four configurations, depending upon the setting of register

0xBF (see the Register Architecture Description section, page 57—page 59).

Table 14. Device Register Map

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Control, Alarm, and Mask Bit Registers

00 00000000

TEST_CNT

B1ERRINS

B2ERRINS

B3ERRINS

LATCH_CNT

BLUECLKSEL

BIPBLKCNT

01 00000001

REI_EN

AUTO_LRDI

TXPAISINS

DJACTL

STS1SCR

STS1DSCR

STS1LB

02 00000010

RXSERIAL

TXSERIAL

RXPARITY

TXPARITY

RXSTS1EDGE TXSTS1EDGE RXDS1EDGE

TXDS1EDGE

03 00000011

TRACEER

RXPARER

H4LOMF

STS1PAIS

STS1LOP

STS1LOF

STS1OOF

04 00000100 TRACEERMSK RXPARERMSK

H4LOMFMSK STS1PAISMSK STS1LOPMSK STS1LOFMSK STS1OOFMSK

05 00000101

ESOFCOM

VTSIZECOM

VTLOPCOM VTRFIRDICOM

VTAISCOM

VTLABCOM

AISLOCCOM

STS1LOS

06 00000110

ESOFMSK

VTSIZEMSK

VTLOPMSK

VTRFIRDIMSK

VTAISMSK

VTLABMSK

AISLOCMSK STS1LOSMSK

07 00000111

0000

DS1_E1N

08 00001000

LATCH_TP

RCV_FRAME

RCV_PAT-1

RCV_PAT-0

ERROR_INS

XMT_FRAME

XMT_PAT-1

XMT_PAT-0

09 00001001 TP_DS1E1N

TP_INVERT

TPDROPSIDE

TPDROP-4

TPDROP-3

TPDROP-2

TPDROP-1

TPDROP-0

0A 00001010

TPOOS

TPERR-6

TPERR-5

TPERR-4

TPERR-3

TPERR-2

TPERR-1

TPERR-0

0B 00001011

F2-7

F2-6

F2-5

F2-4

F2-3

F2-2

F2-1

F2-0

0C 00001100

C2-7

C2-6

C2-5

C2-4

C2-3

C2-2

C2-1

C2-0

0D 00001101

G1-5

G1-6

G1-7

G1-8

K2-6

K2-7

K2-8

0E 00001110

C2#DET-3

C2#DET-2

C2#DET-1

C2#DET-0

F2#DET-3

F2#DET-2

F2#DET-1

F2#DET-0

0F 00001111

G1#DET-3

G1#DET-2

G1#DET-1

G1#DET-0

K2#DET-3

K2#DET-2

K2#DET-1

K2#DET-0

10 00010000

F2INS-7

F2INS-6

F2INS-5

F2INS-4

F2INS-3

F2INS-2

F2INS-1

F2INS-0

11 00010001

G1INS-5

G1INS-6

G1INS-7

G1INS-8

K2INS-6

K2INS-7

K2INS-8

12 00010010

RBUSMODE

RBUSPOS-1

RBUSPOS-0

TBUSMODE

TBUSPOS-1

TBUSPOS-0

13 00010011

S1INS-3

S1INS-2

S1INS-1

S1INS-0

14 00010100

S1#DET-3

S1#DET-2

S1#DET-1

S1#DET-0

S1-3

S1-2

S1-1

S1-0

15 00010101

DEVID-7

DEVID-6

DEVID-5

DEVID-4

DEVID-3

DEVID-2

DEVID-1

DEVID-0

16 00010110

DEVVER-3

DEVVER-2

DEVVER-1

DEVVER-0

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