TMPR28051 datasheet(65/90 Pages) AGERE

65 / 90 page

Data Sheet

August 1999

TMPR28051 STS-1/AU-3 (STM-0) Mapper

Lucent Technologies Inc.

Microprocessor Interface Description (continued)

Tx VT Overhead Insertion Control (0x4F—0x6A)

Table 21. Registers 0x4F—0x6A: Tx VT Overhead Insertion Control

Address

(Hex)

Bit #

Name

Function

Reset

Default

(Hex)

0x4F—0x6A

—

The bits in these registers provision the transmitted VT

overhead byte, V5.

Value is

BIP2ERINS[1:28]

Each BIP2ERINS[1:28] bit = 1 forces the selected VT to

transmit inverted BIP-2 bits which causes the down-

stream receiver to declare continuous BIP-2 errors.

VTRFIRDIEN[1:28] The VTRFIRDIEN[1:28] bits control whether

RDI-V bits are inserted automatically by the device

(VTRFIRDIEN[1:28] = 1) or manually by the

microprocessor (VTRFIRDIEN[1:28] = 0).

VTRFIINS[1:28]

The VTRFIINS[1:28] bits directly program the transmitted

RFI-V bits when the corresponding VTRFIRDIEN[1:28]

bits = 1.

VTRDIINS[1:28]

The VTRDIINS[1:28] bits directly program the transmitted

RDI-V bits when the corresponding VTRFIRDIEN[1:28]

bits = 1.

3VTAISINS[1:28]

Each VTAISINS[1:28] bit = 1 forces AIS-V to be written

into the corresponding VT slot. This consists of writing all

1s into the selected VT slot.

2VTLABINS2_[1:28] The VTLABINS[2:0]_[1:28] bits directly program the

transmitted VT label bits. These bits are used to carry

unequipped information (VTLABINS[2:0]_[1:28] = 000) as

well as specific payload mappings and AIS-V.

1VTLABINS1_[1:28]

0VTLABINS0_[1:28]

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