TMPR28051 datasheet(56/90 Pages) AGERE

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Data Sheet

TMPR28051 STS-1/AU-3 (STM-0) Mapper

August 1999

Lucent Technologies Inc.

Microprocessor Interface Description (continued)

Table 15. Registers 0x00—0x16: Device-Level Control, Alarm, and Mask Bits (continued)

Address

(Hex)

Bit #

Name

Function

Reset

Default

(Hex)

0x06

ESOFMSK

The bits in register 0x06 are used to mask the contributions

of the bits in register 0x05 to the microprocessor interrupt

output, INT. When any of these bits is 1, the corresponding

bit in register 0x05 is masked from contributing to the out-

put interrupt. The reset default for this register masks all of

the bits in register 0x05.

0xFF

VTSIZEMSK

5VTLOPMSK

VTRFIRDIMSK

3VTAISMSK

2VTLABMSK

1AISLOCMSK

STS1LOSMSK

0x07

This register reports the hardware selected device mode.

0x01

7—1

—

Reserved. These bits are set to 0 at reset.

DS1_E1N

This bit reports the DS1_E1N value from the device input

pin.

0x08

The bits in register 0x08 are used to configure the test pat-

tern generator and detector.

0x00

LATCH_TP

A 0 to 1 transition on LATCH_TP causes the running error

count to be latched and presented to the microprocessor.

RCV_FRAME

RCV_FRAME = 1 causes a framed test pattern to be

expected; a 0 causes an unframed test pattern to be

expected.

RCV_PAT-1

RCV_PAT[1:0] determines the receive test pattern

sequence where 00 = QRSS, 01 = 223 – 1,

10 = 2

20 – 1, 11 = 215 – 1.

RCV_PAT-0

ERROR_INS

ERROR_INS causes a single error to be inserted in the

data (not frame) bits after a 0 to 1 transition.

XMT_FRAME

XMT_FRAME = 1 causes a framed test pattern to be gen-

erated; a 0 causes an unframed test pattern to be gener-

ated.

XMT_PAT-1

XMTPAT-[1:0] determines the transmit test pattern

sequence where 00 = QRSS, 01 = 223 – 1,

10 = 220 – 1, 11 = 215 – 1.

XMT_PAT-0

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