| Electronic Components Datasheet Search |
|
TMPR28051 Datasheet(PDF) 73 Page - Agere Systems |
|
|
|||||||||||||||||||||||||||||
TMPR28051 Datasheet(HTML) 73 Page - Agere Systems |
|
73 / 90 page ![]() Data Sheet August 1999 TMPR28051 STS-1/AU-3 (STM-0) Mapper 59 Lucent Technologies Inc. Microprocessor Interface Description (continued) Register Architecture Description (continued) Receive J1 Path Trace Bytes (0xC0—0xFF) Table 31. Registers 0xC0—0xFF: Receive J1 Path Trace Bytes Note: Bits in registers 0xC0—0xFF can have one of four configurations, depending upon the setting of register 0xBF. When register 0xBF is set for BIP_CNTS = 0 and REI_CNTS = 0 and RJ1BYTE = 1, the bytes in reg- isters 0xC0—0xFF are used to read the received 64 path trace bytes. Transmit J1 Path Trace Bytes (0xC0—0xFF) Table 32. Registers 0xC0—0xFF: Transmit J1 Path Trace Bytes Note: Bits in registers 0xC0—0xFF can have one of four configurations, depending upon the setting of register 0xBF. When register 0xBF is set for BIP_CNTS = 0 and RJ1BYTE = 1 and TJ1BYTE = 1, the bytes in regis- ters 0xC0—0xFF are used to provision the transmit 64 path trace bytes. Address (Hex) Bit # Name Function Reset Default (Hex) 0xC0—0xFF 7 RJ1BYTE7_[64:1] The receive J1 path trace byte RJ1BYTE[7:0]_64 corre- sponds to the first byte in the 64-byte sequence, while the J1 path trace byte RJ1BYTE[7:0]_1 corresponds to the last byte in the 64-byte sequence. These specified receive J1 byte values are continuously written, modulo 64, into the 0xC0—0xFF registers. If any received byte does not match the previously received byte for its loca- tion, then TRACEER bit (bit 7) in register 0x03 is set to 1. Value is 0. 6RJ1BYTE6_[64:1] 5RJ1BYTE5_[64:1] 4RJ1BYTE4_[64:1] 3RJ1BYTE3_[64:1] 2RJ1BYTE2_[64:1] 1RJ1BYTE1_[64:1] 0RJ1BYTE0_[64:1] Address (Hex) Bit # Name Function Reset Default (Hex) 0xC0—0xFF 7 TJ1BYTE7_[64:1] The transmit J1 path trace byte TJ1BYTE[7:0]_64 corre- sponds to the first byte in the 64-byte sequence, while the J1 path trace byte TJ1BYTE[7:0]_1 corresponds to the last byte in the 64-byte sequence. These registers can be written by the microprocessor. Value is 0. 6TJ1BYTE6_[64:1] 5TJ1BYTE5_[64:1] 4TJ1BYTE4_[64:1] 3TJ1BYTE3_[64:1] 2TJ1BYTE2_[64:1] 1TJ1BYTE1_[64:1] 0TJ1BYTE0_[64:1] |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |