TMPR28051 datasheet(27/90 Pages) AGERE

27 / 90 page

Data Sheet

August 1999

TMPR28051 STS-1/AU-3 (STM-0) Mapper

Lucent Technologies Inc.

DS1/E1 to STS-1 Block Descriptions

(continued)

VT Generate (continued)

The device would transmit 0 in each of the O bits when

the DS1_E1N pin is pulled high. If DS1_E1N is pulled

low, the device will transmit 1 in each of the O bits.

The R bits are always set to 1.

The device transmits all 1s in the J2, Z6/N2, and Z7/K4

bytes.

The device can be configured such that any detected

BIP-2 errors in the VT receive side result in REI-V

being written into the corresponding transmit VT slot

(when REI_EN = 1 in bit 7 of register 0x01).

STS-1/AU-3 Generate

The device generates an STS-1 signal based on an

incoming clock (TSTS1CLK) and frame sync pulse

(TSTS1SYNC). The frame sync pulse can be a single

clock-period wide to indicate an 8 kHz sync, or it can

contain pulses in three clock periods to indicate a com-

posite 2 kHz sync. (See the Transmit Sync Timing sec-

tion, page 70.)

The STS-1 frame is 9 rows x 90 columns that repeats

at an 8 kHz rate. Each column is 1-byte wide. The

STS-1 frame contains three columns of transport over-

head, one column of path overhead, and 86 columns of

payload.

The 36 bytes of STS-1 overhead are allocated as

shown in Table 6.

Table 6. STS-1 Overhead Byte Allocation

The overhead bytes that are inserted by the device are

described below. All of the remaining overhead bytes

are given a fixed value of all 0s when DS1_E1N (bit 0

in register 0x07) is high, or all 1s when DS1_E1N is

low.

The device inserts the correct frame pattern of 0xF628

into the A1 and A2 bytes.

The device inserts a fixed value of 0x01 into the J0

byte.

The device generates and inserts valid B1, B2, and B3

BIP-8 even parity bytes into the STS-1 overhead.

These bytes are forced to odd parity when

B[1:3]ERRINS = 1 in bit 6 through bit 4 of register 0x00.

The device will provide an STS-1 pointer with a fixed

value of 522 (decimal) with 0110 in the new data flag

(NDF) bits. The SS bits are determined by the level of

the DS1_E1N pin. When this pin is high, the device

puts 00 in the SS bits. When this pin is low, the device

puts 10 in the SS bits. This pointer value indicates that

the J1 path overhead byte follows immediately after the

J0 line overhead byte.

The J1 byte is used for path trace. This byte repetitively

transmits a 64-byte fixed length sequence to verify

end-to-end connectivity. These 64 bytes are program-

mable by the microprocessor by provisioning

TJ1BYTE[7:0]_[64:1] in registers 0xC0—0xFF (when

TJ1BYTE = 1 in register 0xBF). The method for pro-

gramming these bits is described in detail in the regis-

ter description of the transmit J1 path trace bytes,

page 59.

The F2 byte can be provisioned by the microprocessor

(F2INS-[7:0]) in register 0x10.

The device inserts a value of 0x02 into the C2 byte,

indicating VT structured STS-1 SPE.

The three least significant bits of the K2 byte can be

provisioned by the microprocessor (K2INS-[6:8]) in reg-

ister 0x11.

The four least significant bits of the S1 byte can be pro-

visioned by the microprocessor (S1INS-[3:0]) in regis-

ter 0x13.

The M0 byte is used to report B2 line REI (REI-L) when

REI_EN = 1 in register 0x01. This register contains the

number of B2 BIP-8 errors detected in the current

receive frame circuitry when REI_EN = 1 (bit 7 0f regis-

ter 0x01). Valid values for these 4 bits are 0000—1000.

The G1 byte is used to convey path condition and per-

formance back to the far end. The format of the G1

byte is shown in Table 7.

Table 7. G1 Path Condition/Performance Byte

Format

Col. 1

Col. 2

Col. 3

Col. 4

Row 1

Row 2

Row 3

Row 4

Row 5

Row 6

Row 7

Z3/F3

Row 8

D10

D11

D12

Z4/K3

Row 9

Z5/N1

Bit #

1234

678

REI-P

User-Provisioned

RDI-P

TMPR28051 Datasheet(PDF) 27 Page - Agere Systems

TMPR28051 Datasheet(HTML) 27 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

Datasheet Download

Link URL