TMPR28051 datasheet(33/90 Pages) AGERE

33 / 90 page

Data Sheet

August 1999

TMPR28051 STS-1/AU-3 (STM-0) Mapper

Lucent Technologies Inc.

Test Pattern Block Descriptions

The device contains a test pattern generator and a test

pattern detector for use in maintenance and trouble-

shooting.

Test Pattern Insert

The test pattern generator is capable of transmitting

four different test patterns (XMT_PAT-[1:0] in bit posi-

tions 0 and 1 of register 0x08). In addition to a 215 – 1,

a 220 – 1, and a 223 – 1 sequence, the device can also

transmit a QRSS sequence. The QRSS pattern is a

220 – 1 pseudorandom bit sequence defined by the

equation 1 + x17 + x20 = 0, with a 14 zero limit.

As can be seen in Figure 1 on page 5, this test pattern

can be inserted in the place of any of the transmitted or

received DS1/E1 signals. The test pattern can also be

provisioned to be framed (XMT_FRAME = 1 in bit 2 of

of register 0x08). The framed sequence can be either

DS1 SF format (TP_DS1E1N = 1 in bit 7 of register

0x09) or E1 format (TP_DS1E1N = 0 in bit 7 of register

0x09). The test pattern can also be forced to transmit a

bit error (ERROR_INS bit in register 0x08, bit position

3, is forced to make low to high transition). The test

patterns are O.151 compliant, so they can be used to

drive external test equipment as well as to perform

internal maintenance and troubleshooting.

Test Pattern Drop

The test pattern detector can detect the same four test

sequences generated by the test pattern generator

(RCV_PAT-[1:0] in bit positions 4 and 5 of register

0x08). When the detector is out of synchronization, the

device continuously monitors the input data signal for

matches with the expected data signal. When the

device detects 32 matches in a row, it declares itself in

sync (TPOOS = 0 in bit 7 of register 0x0A), and the

error detector is enabled. If the device detects eight

consecutive bit mismatches, the test pattern detector

declares itself out of sync (TPOOS = 1), and starts

searching again.

The test pattern detector can be configured to look for

a framed (RCV_FRAME = 1 in bit 6 of register 0x08) or

unframed (RCV_FRAME = 0 in bit 6 of register 0x08)

signal.

While in sync, the device counts the number of times

the input data differs from the expected data in a 7-bit

counter, TPERR-[6:0] (bit 0 through bit 6 in register

0x0A), that holds its count when it reaches the maxi-

mum value of 128. This counter is reset when the

LATCH_TP bit (bit 7) in register 0x08 makes a 0 to 1

transition.

TMPR28051 Datasheet(PDF) 33 Page - Agere Systems

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