TMPR28051 datasheet(22/90 Pages) AGERE

22 / 90 page

Data Sheet

TMPR28051 STS-1/AU-3 (STM-0) Mapper

August 1999

Lucent Technologies Inc.

Pin Information (continued)

Table 1. Pin Descriptions (continued)

* Iu indicates an internal pull-up; Id indicates an internal pull-down. All I/O not explicitly stated with a buffer type are 5 V TTL compatible; they will

tolerate 5 V at their inputs.

Symbol

Type*

Name/Description

179

MPMUX

Microprocessor Multiplex Mode. Setting MPMUX = 1 allows the micropro-

cessor interface to accept the multiplexed address and data signals. Setting

MPMUX = 0 allows the microprocessor interface to accept demultiplexed

(separate) address and data signals.

180

MPMODE

Microprocessor Mode. When MPMODE = 1, the device uses the address

latch enable type microprocessor read/write protocol with separate read and

write controls. Setting MPMODE = 0 allows the device to use the address

strobe type microprocessor read/write protocol with a separate data strobe

and a combined read/write control.

181

RD_R/W

Read (Active-Low). If MPMODE = 1, this pin is asserted low by the micropro-

cessor to initiate a read cycle.

Read/Write. If MPMODE = 0, this pin is asserted high by the microprocessor

to indicate a read cycle or asserted low to indicate a write cycle.

178

ALE_AS

Address Latch Enable. If MPMODE = 1, this pin becomes the address latch

enable for the microprocessor. When this pin transitions from high to low, the

address bus inputs are latched into the internal registers.

Address Strobe (Active-Low). If MPMODE = 0, this pin becomes the

address strobe for the microprocessor. When this pin transitions from high to

low, the address bus inputs are latched into the internal registers.

Chip Select (Active-Low). This pin is asserted low by the microprocessor to

enable the microprocessor interface (see Microprocessor Configuration

Modes section on page20). This pin has an internal 100 k

Ω pull-up resistor.

INT

Interrupt. This pin is asserted high to indicate an interrupt produced by an

alarm condition in register 3 or 5. The activation of this pin can be masked by

microprocessor registers 4 and 6.

183

RDY_DTACK

Ready. If MPMODE = 1, this pin is asserted high to indicate the device has

completed a read or write operation. This pin is in a high-impedance state

when CS is high.

Data Transfer Acknowledge (Active-Low). If MPMODE = 0, this pin is

asserted low to indicate the device has completed a read or write operation.

48—50,

55—59

AD[7:0]

I/O

Microprocessor Interface Address/Data Bus. If MPMUX = 0, these pins

become the bidirectional, 3-statable data bus. If MPMUX = 1, these pins

become the multiplexed address/data bus.

60—64,

66—68

A[7:0]

Microprocessor Interface Address. If MPMUX = 0, these pins become the

address bus for the microprocessor interface registers.

176

WR_DS

Write (Active-Low). If MPMODE = 1, this pin is asserted low by the micro-

processor to initiate a write cycle.

Data Strobe (Active-Low). If MPMODE = 0, this pin becomes the data

strobe for the microprocessor. When R/W = 0 (write), a low applied to this pin

latches the signal on the data bus into internal registers.

106

RESET

Hardware Reset (Active-Low). If RESET is forced low, all internal states in

the transceiver paths are reset and data flow through each channel will be

interrupted (see Device-Level Control, Alarm, and Mask Bits (0x00—0x16)

section on page37). This pin has an internal 20 k

Ω pull-up resistor.

184

TCK

Boundary-Scan Clock. This pin has an internal 20 k

Ω pull-up resistor.

TMPR28051 Datasheet(PDF) 22 Page - Agere Systems

TMPR28051 Datasheet(HTML) 22 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

Datasheet Download

Link URL