TMPR28051 datasheet(57/90 Pages) AGERE

57 / 90 page

Data Sheet

August 1999

TMPR28051 STS-1/AU-3 (STM-0) Mapper

Lucent Technologies Inc.

Microprocessor Interface Description (continued)

Table 15. Registers 0x00—0x16: Device-Level Control, Alarm, and Mask Bits (continued)

Address

(Hex)

Bit #

Name

Function

Reset

Default

(Hex)

0x09

—

The bits in register 0x09 are used to set up the test pattern.

0x00

TP_DS1E1N

TP_DS1E1N = 1 sets the frame sequence to DS1;

TP_DS1E1N = 0 sets the frame sequence to E1.

TP_INVERT

TP_INVERT = 1 forces the test pattern sequence to be

inverted.

TPDROPSIDE

When TPDROPSIDE = 1, the test pattern is dropped from

the SPE drop logic. The DS1/E1 output that is dropped is

described in the Microprocessor Interface Description (con-

tinued) section on page 50. When TPDROPSIDE = 0, the

DS1/E1 that is dropped is the same as described in the

DS1/E1 Insertion Selection section on page47.

TPDROP-4

The TPDROP[4:0] bits are used to select the VT that needs

to be dropped.

3TPDROP-3

2TPDROP-2

1TPDROP-1

0TPDROP-0

0x0A

—

The bits in register 0x0A indicate the condition of the test

pattern detector.

0x80

TPOOS

If the test pattern detector has been able to synchronize on

the dropped signal, then TPOOS = 0.

TPERR-6

When TPOOS = 0, then the TPERR-[6:0] bits are used to

keep count of the number of bit errors the test pattern

detector has seen. This error count is cleared when the

5TPERR-5

4TPERR-4

3TPERR-3

2TPERR-2

1TPERR-1

0TPERR-0

0x0B

7—0

F2-[7:0]

The F2-[7:0] bits in register 0x0B are used to report the F2

receive byte in the path overhead.

0x00

0x0C

7—0

C2-[7:0]

The C2-[7:0] bits in register 0x0C are used to report the

received C2 label byte in the path overhead. The default

value for this register indicates path unequipped.

0x00

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