TMPR28051 datasheet(62/90 Pages) AGERE

62 / 90 page

Data Sheet

TMPR28051 STS-1/AU-3 (STM-0) Mapper

August 1999

Lucent Technologies Inc.

Microprocessor Interface Description (continued)

Table 16. Registers 0x17—0x32: DS1/E1 Insertion Selection (continued)

Address

(Hex)

Bit #

Name

Function

Reset

Default

(Hex)

0x2C—0x32

—

Registers 0x17—0x32 report DS1 conditions.

Value is

DS1AIS[22:28]

The DS1/E1AIS[1:21] and DS1AIS[22:28] bits report the

received DS1 AIS condition. When any of these bits is 1,

the corresponding DS1 input has an AIS condition. This

value represents the current received state. The AIS condi-

tion is not latched by these bits. The indication is reset

when the condition is no longer true.

DS1LOC[22:28]

The DS1/E1LOC[1:21] and DS1LOC[22:28] bits in bit 6

report the received DS1 loss of clock condition. When any

of these bits is 1, the corresponding DS1 input has a

received loss of clock condition. This value represents the

current received state. The loss of clock condition is not

latched by these bits. The indication is reset when the con-

dition is no longer true.

DS1LB[22:28]

The DS1/E1LB[1:21] and DS1LB[22:28] bits in bit 5 are

used to force DS1 loopback from output to input. When any

of these bits is 1, the corresponding DS1 input is overwrit-

ten by the outgoing DS1 signal for that location.

DS1INS4_[22:28] The DS1/E1INS[4:0]_[1:21] and DS1INS[4:0]_[22:28] bits

in registers 0x17—0x32 are used to select the DS1 input

for the transmit VT1.5 slots. The DS1 selected corresponds

to the decimal value of the programmed 5 bits. If these bits

contain 00000, the device will insert unequipped into the

corresponding VT1.5 slot. If these bits contain 11101—

11110, the device will insert AIS-V into the corresponding

VT1.5 slot. Since the device defaults all 28 of these regis-

ters to the value 00000, all of the 28 VT1.5 slots begin

transmitting unequipped following reset. The value 11111

inserts the test pattern. Addresses 0x17—0x32 correspond

to VT1.5s as shown in Table 17, page 49.

DS1INS3_[22:28]

DS1INS2_[22:28]

DS1INS1_[22:28]

DS1INS0_[22:28]

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