TMPR28051 datasheet(53/90 Pages) AGERE

53 / 90 page

Data Sheet

August 1999

TMPR28051 STS-1/AU-3 (STM-0) Mapper

Lucent Technologies Inc.

Microprocessor Interface Description (continued)

Table 15. Registers 0x00—0x16: Device-Level Control, Alarm, and Mask Bits (continued)

Address

(Hex)

Bit #

Name

Function

Reset

Default

(Hex)

0x02

—

The bits in register 0x02 are used to set the edges that

retime data into and out of the device.

0x00

RXSERIAL

Receive Serial Data, Transmit Serial Data. Both the

RXSERIAL and TXSERIAL bits are used to set the type of

STS-1 data. When either serial bit is written to 1, the STS-1

rail runs in serial mode; otherwise, the STS-1 rail runs in

parallel mode.

TXSERIAL

RXPARITY

Both the RXPARITY and TXPARITY bits determine the

type of parity for data buses. When these bits are written

with 1, odd parity is used; otherwise, even parity is used.

TXPARITY

RXSTS1EDGE

When the edge register bits are set to 1, the data is retimed

(either in or out) by the rising clock edge; when set to a

logic 0, the data is retimed by the falling clock edge. Note

that the TSTS1SERIAL data always comes out on the ris-

ing edge of the TSTS1CLKOUT.

Note: The TXSTS1EDGE (bit 2) should always be set to 0

to avoid potential race condition inside the device.

2TXSTS1EDGE

RXDS1EDGE

TXDS1EDGE

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