TMPR28051 datasheet(19/90 Pages) AGERE

19 / 90 page

Data Sheet

August 1999

TMPR28051 STS-1/AU-3 (STM-0) Mapper

Lucent Technologies Inc.

Description (continued)

On the STS-1 side, the device can be configured for either a serial bit stream or an 8-bit parallel bus. This allows

the device to drive an OC-1 optical signal directly and also allows for modular growth in terminal or add/drop appli-

cations.

On the DS1/E1 side, the device is designed to interface with the Lucent T7698FL3/T7693 Quad Line Transceiver,

or equivalent, using the internal digital jitter attenuator buffer for PLL-free operation.

The TMPR28051 device contains built-in test pattern insertion and drop that allows end-to-end testing for initial

setup or maintenance without the need for external test equipment. Built-in loopbacks at both the STS-1 and DS1/

E1 sides provide maximum flexibility for use in a number of SONET/SDH or DS1/E1 products including terminal

multiplexers, add/drop multiplexers, and digital cross connects. A high-speed microprocessor interface and full

user programmability for VT slot insertion and drop provide maximum flexibility for DS1/E1 I/O configuration.

Block Diagram

The block diagram is shown in Figure 1. For illustration purposes, only two of the DS1/E1 bidirectional blocks are

shown.

5-4875(F).ar.10

Note: “n” represents 28 or 21 for DS1 or E1, respectively.

Figure 1. Block Diagram

MICROPROCESSOR

INTERFACE

STS-1/AU-3

TERMINATE

DS1/E1 #1 IN

ELASTIC

STORE

SPE

INSERTION

LOGIC

GENERATE

ELASTIC

STORE

GENERATE

DS1/E1 #n IN

STS-1/AU-3

GENERATE

DS1/E1 #1 OUT

SPE

DROP

LOGIC

TERMINATE

DS1/E1 #n OUT

STS-1/AU-3 IN

INPUT

SELECT

LOGIC

LOOP-

SELECT

LOGIC

INPUT

SELECT

LOGIC

SPE

LOCATE

DROP

SELECT

LOGIC

LOC AND

TEST

PATTERN

INSERT

TEST

PATTERN

DROP

BACK

LOOP-

SELECT

LOGIC

BACK

DROP

SELECT

LOGIC

LOOP-

SELECT

LOGIC

BACK

STS-1/AU-3 OUT

AIS

MONITOR

LOC AND

AIS

MONITOR

JITTER

ATTENUATE

JITTER

ATTENUATE

TMPR28051 Datasheet(PDF) 19 Page - Agere Systems

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