TMPR28051 datasheet(74/90 Pages) AGERE

74 / 90 page

Data Sheet

TMPR28051 STS-1/AU-3 (STM-0) Mapper

August 1999

Lucent Technologies Inc.

Microprocessor Interface Description (continued)

I/O Timing

The I/O timing specifications for the microprocessor interface are given in Table 33. The microprocessor interface

pins use CMOS I/O levels (see pages 20—22 for pin listings). All outputs, except the address/data bus AD[7:0], are

rated for a capacitive load of 50 pF. The AD[7:0] outputs are rated for a 100 pF load. The minimum read and write

cycle time is 200 ns for all device configurations.

The read and write timing diagrams for all four microprocessor interface modes are shown in Figures 3—10.

Table 33. Microprocessor Interface I/O Timing Specifications

Symbol

Configuration

Parameter

Setup

(ns)

(Min)

Hold

(ns)

(Min)

Delay

(ns)

(Max)

Modes 1 & 2

Address Valid to AS Asserted (Read, Write)

5—

—

AS Asserted to Address Invalid (Read, Write)

—10

—

AS Asserted to DS Asserted

—

R/W High (Read) to DS Asserted

—

DS Asserted (Read, Write) to DTACK Asserted

—

DTACK Asserted to Data Valid (Read)

——

DS Asserted (Read) to Data Valid

—

DS Negated (Read, Write) to AS Negated

—

DS Negated (Read) to Data Invalid

—

t10

DS Negated (Read) to DTACK Negated

—

t11

AS (Read, Write) Asserted Width

—

t12

DS (Read) Asserted Width

—

t13

AS Asserted to R/W Low (Write)

7—

—

t14

R/W Low (Write) to DS Asserted

—

t15

Data Valid to DS Asserted (Write)

7.5

—

t16

DS Negated to DTACK Negated (Write)

——

t17

DS Negated to Data Invalid (Write)

—7.5

—

t18

DS (Write) Asserted Width

—

t19

Modes 3 & 4

Address Valid to ALE Asserted Low (Read, Write)

—

t20

ALE Asserted Low (Read, Write) to Address Invalid

—

t21

ALE Asserted Low to RD Asserted (Read)

—

t22

RD Asserted (Read) to Data Valid

—

t23

RD Asserted (Read) to RDY Asserted

—

t24

RD Negated to Data Invalid (Read)

——

t25

RD Negated to RDY Negated (Read)

——

t26

ALE Asserted Low to WR Asserted (Write)

—

t27

CS Asserted to RDY Asserted Low

—

t28

Data Valid to WR Asserted (Write)

—

t29

WR Asserted (Write) to RDY Asserted

—

t30

WR Negated to RDY Negated (Write)

——

t31

WR Negated to Data Invalid

—

t32

ALE Asserted (Read, Write) Width

—

150

—

t33

RD Asserted (Read) Width

—

100

—

t34

WR Asserted (Write) Width

—

100

—

TMPR28051 Datasheet(PDF) 74 Page - Agere Systems

TMPR28051 Datasheet(HTML) 74 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

Datasheet Download

Link URL