TMPR28051 datasheet(69/90 Pages) AGERE

69 / 90 page

Data Sheet

August 1999

TMPR28051 STS-1/AU-3 (STM-0) Mapper

Lucent Technologies Inc.

Microprocessor Interface Description (continued)

Table 25. Register 0x91: STS-1 LOS Detect/Test Pattern Edge Control

Address

(Hex)

Bit #

Name

Function

Reset

Default

(Hex)

0x91

—

The bits in register 0x91 are used to set the number of

6.48 MHz clock periods required to declare received STS-1

loss of signal. The two least significant bits have a dual pur-

pose and can also be used to program the edge on which

the QRSS pattern generator and detector data is clocked.

If this value is 0x00, then LOS is not declared; otherwise,

the device looks for an all-zeros or all-ones input signal for

the binary equivalent of this value in clock periods to

declare LOS.

0x00

LOSDET-7

These bits are used to set the number of 6.48 MHz clock

periods required to declare received STS-1 loss of signal.

6LOSDET-6

5LOSDET-5

4LOSDET-4

3LOSDET-3

2LOSDET-2

1LOSDET-1/

TP_EDGE-1

This bit has a dual purpose. It can either contribute to the

above count or can be programmed to set the edge on

which the test pattern detector data is clocked in. When set

to 0, the detector uses the rising edge of the selected input

clock to retime the data, or uses the falling edge otherwise.

0LOSDET-0/

TP_EDGE-0

This bit has a dual purpose. It can either contribute to the

above count or can be programmed to set the edge on

which the test pattern generator data is clocked out. When

set to 0, the generator uses the rising edge of the blue sig-

nal clock to retime the data, or uses the falling edge other-

wise.

0x92—0xBE

7—0

—

Reserved.

Value is

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