TMPR28051 datasheet(18/90 Pages) AGERE

18 / 90 page

Data Sheet

TMPR28051 STS-1/AU-3 (STM-0) Mapper

August 1999

Lucent Technologies Inc.

List of Tables

Tables

Page

Table 1. Pin Descriptions ......................................................................................................................................... 7

Table 2. VT1.5 Overhead Byte Format (V5) .......................................................................................................... 11

Table 3. RFI-V, RDI-V Description ........................................................................................................................ 11

Table 4. VT1.5 Superframe ................................................................................................................................... 12

Table 5. VT2 Superframe ...................................................................................................................................... 12

Table 6. STS-1 Overhead Byte Allocation ............................................................................................................. 13

Table 7. G1 Path Condition/Performance Byte Format ......................................................................................... 13

Table 8. VT1.5 SPE Insertion Format .................................................................................................................... 15

Table 9. Mapping of VT1.5 # to (VT Group #, VT #) .............................................................................................. 15

Table 10. VT2 SPE Insertion Format ..................................................................................................................... 15

Table 11. Mapping of VT2 # to (VT Group #, VT #) ............................................................................................... 15

Table 12. Microprocessor Configuration Modes .................................................................................................... 20

Table 13. Mode [1—4] Microprocessor Pin Definitions ......................................................................................... 21

Table 14. Device Register Map ............................................................................................................................. 23

Table 15. Registers 0x00—0x16: Device-Level Control, Alarm, and Mask Bits .................................................... 37

Table 16. Registers 0x17—0x32: DS1/E1 Insertion Selection ............................................................................. 47

Table 17. DS1/E1 Insertion Selection Format ....................................................................................................... 49

Table 18. Registers 0x33—0x4E: VT Drop Selection ............................................................................................49

Table 19. VT Drop Selection Format ..................................................................................................................... 50

Table 20. VT to Address Mapping ......................................................................................................................... 50

Table 21. Registers 0x4F—0x6A: Tx VT Overhead Insertion Control ................................................................... 51

Table 22. Registers 0x6B—0x86: Rx VT Drop Monitoring .................................................................................... 52

Table 23. Registers 0x88—0x89: Signal Override Control .................................................................................... 53

Table 24. Registers 0x8A—0x8F: Digital Jitter Attenuator Controls ...................................................................... 54

Table 25. Register 0x91: STS-1 LOS Detect/Test Pattern Edge Control .............................................................. 55

Table 26. Register 0xBF: Block Control ................................................................................................................ 56

Table 27. Registers 0xC0—0xFD: Detected BIP Errors ........................................................................................ 57

Table 28. Registers 0xFE, 0xFF: Received SONET/SDH Pointer Value .............................................................. 57

Table 29. Registers 0xC0—0xFD: Detected REI Errors ........................................................................................ 58

Table 30. Registers 0xFE—0xFF: Reserved ......................................................................................................... 58

Table 31. Registers 0xC0—0xFF: Receive J1 Path Trace Bytes .......................................................................... 59

Table 32. Registers 0xC0—0xFF: Transmit J1 Path Trace Bytes ......................................................................... 59

Table 33. Microprocessor Interface I/O Timing Specifications .............................................................................. 60

Table 34. Absolute Maximum Ratings ................................................................................................................... 65

Table 35. ESD Threshold Voltage ......................................................................................................................... 65

Table 36. Recommended Operating Conditions ................................................................................................... 66

Table 37. Logic Interface Characteristics .............................................................................................................. 66

Table 38. Input Clock Specifications ..................................................................................................................... 67

Table 39. Input Timing Specifications .................................................................................................................... 68

Table 40. Output Clock Specifications ................................................................................................................... 69

Table 41. Output Timing Specifications ................................................................................................................. 69

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