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WM5102 Datasheet(PDF) 191 Page - Wolfson Microelectronics plc

Part # WM5102
Description  Audio Hub CODEC with Voice Processor DSP
PDF  334 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM5102 Datasheet(HTML) 191 Page - Wolfson Microelectronics plc

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Production Data
WM5102
w
PD, June 2014, Rev 4.2
191
REGISTER
ADDRESS
LABEL
REFERENCE
0D53h
IM_MICD_CLAMP_FALL_EINT1
See “Interrupts”
IM_MICD_CLAMP_RISE_EINT1
IM_GP5_FALL_EINT1
IM_GP5_RISE_EINT1
IM_JD1_FALL_EINT1
IM_JD1_RISE_EINT1
0D54h
IM_MICD_CLAMP_FALL_EINT2
See “Interrupts”
IM_MICD_CLAMP_RISE_EINT2
IM_GP5_FALL_EINT2
IM_GP5_RISE_EINT2
IM_JD1_FALL_EINT2
IM_JD1_RISE_EINT2
0D56h
MICD_CLAMP_DB
See “External Accessory Detection”
JD1_DB
3000h to
31FFh
WSEQ_DATA_WIDTHn
See “Control Write Sequencer”
WSEQ_ADDRn
WSEQ_DELAYn
WSEQ_DATA_STARTn
WSEQ_DATAn
Table 80 Sleep Mode ‘Always-On’ Control Registers
The ‘Always-On’ digital input / output pins are listed in Table 81. All other digital input pins will have no
effect in Sleep mode. The IRQ
¯¯¯ output is normally de-asserted in Sleep mode.
Note that, in Sleep mode, the IRQ
¯¯¯ output can only be asserted in response to the JD1 or GP5 control
signals (these described in the following section). If the IRQ
¯¯¯ output is asserted in Sleep mode, it can
only be de-asserted after a Wake-Up transition.
PIN NAME
DESCRIPTION
REFERENCE
LDOENA
Enable pin for LDO1
See “Charge Pumps, Regulators and
Voltage Reference”
RESET
¯¯¯¯¯¯
Digital Reset input (active low)
See “Software Reset, Wake-Up, and Device
ID”
MCLK2
Master clock 2
See “Clocking and Sample Rates”
GPIO5
General Purpose pin GPIO5
See “General Purpose Input / Output”
IRQ
¯¯¯
Interrupt Request (IRQ) output
See “Interrupts”
Table 81 Sleep Mode ‘Always-On’ Digital Input Pins
A Wake-Up transition is triggered using the JD1 or GP5 control signals (defined below).
It is assumed that DCVDD is supplied by LDO1. The AVDD, DBVDD1 and LDOVDD supplies must be
present throughout the Sleep mode duration. See “Charge Pumps, Regulators and Voltage
Reference” for specific control requirements where DCVDD is not powered from LDO1.
Note that a logic ‘1’ applied to the LDOENA pin will also cause a Wake-Up transition. In this event,
however, the configurable Wake-Up events (described below) are not applicable.



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