WM5102 datasheet(195/334 Pages) WOLFSON

195 / 334 page

Production Data

WM5102

PD, June 2014, Rev 4.2

195

WRITE SEQUENCE CONTROL

A Control Write Sequence can be associated with any of the JD1, GP5 or MICDET Clamp trigger

status bits. This is selected using the register bits described in Table 84.

Note that the JD1, GP5 or MICDET Clamp trigger status bits can only be used to trigger the Control

Write Sequencer during normal operation - it is not possible to trigger the Control Write Sequencer

from the same event used to trigger a Wake-Up transition.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R65 (0041h)

Sequence

Control

WSEQ_ENA_MICD_CL

AMP_FALL

MICDET Clamp (Falling) Write

Sequencer Select

0 = Disabled

1 = Enabled

WSEQ_ENA_MICD_CL

AMP_RISE

MICDET Clamp (Rising) Write

Sequencer Select

0 = Disabled

1 = Enabled

WSEQ_ENA_GP5_FAL

GP5 (Falling) Write Sequencer

Select

0 = Disabled

1 = Enabled

WSEQ_ENA_GP5_RIS

GP5 (Rising) Write Sequencer

Select

0 = Disabled

1 = Enabled

WSEQ_ENA_JD1_FALL

JD1 (Falling) Write Sequencer

Select

0 = Disabled

1 = Enabled

WSEQ_ENA_JD1_RISE

JD1 (Rising) Write Sequencer

Select

0 = Disabled

1 = Enabled

Table 84 JD1, GP5 and MICDET Clamp Write Sequencer Control Registers

When a valid ‘Write Sequencer’ control event is detected, the respective control sequence will be

scheduled. See “Control Write Sequencer” for further details.

If desired, the Control Write Sequencer can be programmed to select the Sleep mode by writing ‘0’ to

the LDO1_ENA bit. (The LDOENA pin must not be asserted.)

See “Charge Pumps, Regulators and Voltage Reference” for details of the LDO1_ENA control bit.

INTERRUPT CONTROL

An Interrupt Request (IRQ) event can be associated with the JD1, GP5 or MICDET Clamp signals.

Separate ‘mask’ bits are provided to enable IRQ events on the rising and/or falling edges of each

signal.

See “Interrupts” for further details.

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