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WM5102 Datasheet(PDF) 308 Page - Wolfson Microelectronics plc |
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WM5102 Datasheet(HTML) 308 Page - Wolfson Microelectronics plc |
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308 / 334 page  WM5102 Production Data w PD, June 2014, Rev 4.2 308 REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R3364 (D24h) Interrupt Raw Status 6 0 0 PWM_ OVER CLOC KED_ STS FX_C ORE_ OVER CLOC KED_ STS 0 DAC_ SYS_ OVER CLOC KED_ STS DAC_ WARP _OVE RCLO CKED _STS ADC_ OVER CLOC KED_ STS MIXER _OVE RCLO CKED _STS AIF3_ ASYN C_OV ERCL OCKE D_STS AIF2_ ASYN C_OV ERCL OCKE D_STS AIF1_ ASYN C_OV ERCL OCKE D_STS AIF3_ SYNC _OVE RCLO CKED _STS AIF2_ SYNC _OVE RCLO CKED _STS AIF1_ SYNC _OVE RCLO CKED _STS PAD_ CTRL_ OVER CLOC KED_ STS 0000h R3365 (D25h) Interrupt Raw Status 7 SLIMB US_S UBSY S_OV ERCL OCKE D_STS SLIMB US_A SYNC _OVE RCLO CKED _STS SLIMB US_S YNC_ OVER CLOC KED_ STS ASRC _ASY NC_S YS_O VERC LOCK ED_ST S ASRC _ASY NC_W ARP_ OVER CLOC KED_ STS ASRC _SYN C_SY S_OV ERCL OCKE D_STS ASRC _SYN C_WA RP_O VERC LOCK ED_ST S 0 0 0 0 0 DSP1_ OVER CLOC KED_ STS 0 ISRC2 _OVE RCLO CKED _STS ISRC1 _OVE RCLO CKED _STS 0000h R3366 (D26h) Interrupt Raw Status 8 0 0 0 0 0 AIF3_ UNDE RCLO CKED _STS AIF2_ UNDE RCLO CKED _STS AIF1_ UNDE RCLO CKED _STS 0 ISRC2 _UND ERCL OCKE D_STS ISRC1 _UND ERCL OCKE D_STS FX_U NDER CLOC KED_ STS ASRC _UND ERCL OCKE D_STS DAC_ UNDE RCLO CKED _STS ADC_ UNDE RCLO CKED _STS MIXER _UND ERCL OCKE D_STS 0000h R3392 (D40h) IRQ Pin Status 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ2_ STS IRQ1_ STS 0000h R3393 (D41h) ADSP2 IRQ0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSP_I RQ2 DSP_I RQ1 0000h R3408 (D50h) AOD wkup and trig 0 0 0 0 0 0 0 0 MICD_ CLAM P_FAL L_TRI G_ST S MICD_ CLAM P_RIS E_TRI G_ST S GP5_F ALL_T RIG_S TS GP5_ RISE_ TRIG_ STS JD1_F ALL_T RIG_S TS JD1_R ISE_T RIG_S TS 0 0 0000h R3409 (D51h) AOD IRQ1 0 0 0 0 0 0 0 0 MICD_ CLAM P_FAL L_EIN T1 MICD_ CLAM P_RIS E_EIN T1 GP5_F ALL_E INT1 GP5_ RISE_ EINT1 JD1_F ALL_E INT1 JD1_R ISE_EI NT1 0 0 0000h R3410 (D52h) AOD IRQ2 0 0 0 0 0 0 0 0 MICD_ CLAM P_FAL L_EIN T2 MICD_ CLAM P_RIS E_EIN T2 GP5_F ALL_E INT2 GP5_ RISE_ EINT2 JD1_F ALL_E INT2 JD1_R ISE_EI NT2 0 0 0000h R3411 (D53h) AOD IRQ Mask IRQ1 0 0 0 0 0 0 0 0 IM_MI CD_CL AMP_ FALL_ EINT1 IM_MI CD_CL AMP_ RISE_ EINT1 IM_GP 5_FAL L_EIN T1 IM_GP 5_RIS E_EIN T1 IM_JD 1_FAL L_EIN T1 IM_JD 1_RIS E_EIN T1 0 0 003Ch R3412 (D54h) AOD IRQ Mask IRQ2 0 0 0 0 0 0 0 0 IM_MI CD_CL AMP_ FALL_ EINT2 IM_MI CD_CL AMP_ RISE_ EINT2 IM_GP 5_FAL L_EIN T2 IM_GP 5_RIS E_EIN T2 IM_JD 1_FAL L_EIN T2 IM_JD 1_RIS E_EIN T2 0 0 003Ch R3413 (D55h) AOD IRQ Raw Status 0 0 0 0 0 0 0 0 0 0 0 0 MICD_ CLAM P_STS GP5_S TS 0 JD1_S TS 0000h R3414 (D56h) Jack detect debounce 0 0 0 0 0 0 0 0 0 0 0 0 MICD_ CLAM P_DB 0 0 JD1_D B 0000h R3584 (E00h) FX_Ctrl1 0 FX_RATE [3:0] 0 0 0 0 0 0 0 0 0 0 0 0000h R3585 (E01h) FX_Ctrl2 FX_STS [11:0] 0 0 0 0 0000h R3600 (E10h) EQ1_1 EQ1_B1_GAIN [4:0] EQ1_B2_GAIN [4:0] EQ1_B3_GAIN [4:0] EQ1_E NA 6318h R3601 (E11h) EQ1_2 EQ1_B4_GAIN [4:0] EQ1_B5_GAIN [4:0] 0 0 0 0 0 EQ1_ MODE 6300h |
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