PM8313 datasheet(114/192 Pages) PMC

114 / 192 page

PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

104

Bit

Type

Function

Default

Bit4

R/W

M3O8

Bit3

R/W

UNI

Bit2

R/W

REFR

Bit1

R/W

AISC

Bit0

R/W

CBE

CBE:

The CBE bit selects whether the C-bit parity application is enabled. When a

logic 1 is written to CBE, C-bit parity mode is enabled. When a logic 0 is

written, C-bit parity mode is disabled.

AISC:

The AISC bit controls the algorithm used to detect the alarm indication signal

(AIS). When a logic 1 is written to AISC, the algorithm checks that a framed

DS3 signal with all C-bits set to logic 0 is observed for a period of time before

declaring AIS. The payload contents are checked to the pattern selected by

the AISPAT bit. When a logic 0 is written to AISC, the AIS detection algorithm

is determined solely by the settings of AISPAT and AISONES register bits

(see bit mapping table in the Additional Configuration Register description).

REFR:

The REFR bit is used to trigger reframing. If a logic 1 is written to REFR

when it was previously logic 0, the FRMR is forced out-of-frame, and a new

search for frame alignment is initiated. Note that only a low to high transition

of the REFR bit triggers reframing; multiple write operations are required to

ensure such a transition.

UNI:

The UNI bit is used to configure the FRMR to accept either unipolar or bipolar

data streams. When a logic 1 is written to UNI, the FRMR accepts unipolar

data and line code violation indication on its inputs. When a logic 0 is written

to UNI, the FRMR accepts bipolar data on its inputs and performs B3ZS

decoding and line code violation reporting.

PM8313 Datasheet(PDF) 114 Page - PMC-Sierra, Inc

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