PM8313 datasheet(117/192 Pages) PMC

117 / 192 page

PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

107

IDLE:

The IDLE bit enables an interrupt to be generated when a change of state of

the DS3 IDLE signal detector occurs. When IDLE is set to logic 1, the

interrupt output, INTB, is set low when the state of the IDLE detector

changes.

FERFE:

The FERFE bit enables an interrupt to be generated when a change of state

of the FERF indication occurs. The FERF indication is visible in the FERFV

bit location of the DS3 FRMR Status register and on the RFERF pin. When

FERFE is set to logic 1, the interrupt output, INTB, is set low when the state

of the FERF output changes.

CBITE:

The CBITE bit enables an interrupt to be generated when change of state in

the C-bit Identification indication internal to the DS3 FRMR occurs. When

CBITE is set to logic 1, the interrupt output, INTB, is set low when the state of

the C-bit Identification indication changes.

REDE:

The REDE bit enables an interrupt to be generated when a change of state of

the DS3 RED indication occurs. The DS3 RED indication is visible in the

REDV bit location of the DS3 FRMR Status register and on the ROOF/RRED

pin when the REDO bit in the Master Alarm Enable register ( register 06Hex)

is set to logic 1. When REDE is set to logic 1, the interrupt output, INTB, is set

low when the state of the RED indication changes.

COFAE:

The COFAE bit enables an interrupt to be generated when a change of frame

alignment (i.e. a COFA event ) occurs. When COFAE is set to logic 1, the

interrupt output, INTB, is set low when the COFA event occurs.

A FRMR-generated interrupt is cleared when the FRMR Interrupt Status Register

is read.

PM8313 Datasheet(PDF) 117 Page - PMC-Sierra, Inc