LAN9250 datasheet(341/421 Pages) MICROCHIP

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DS00001913A-page 341

LAN9250

14.8.19

1588 PORT LATENCY REGISTER (1588_LATENCY)

Note:

Port and GPIO registers share a common address space. Port registers are selected by the Bank Select

(BANK_SEL[2:0] in the 1588 Bank Port GPIO Select Register (1588_BANK_PORT_GPIO_SEL).

Note 2:

The default value is appropriate for 100BASE-TX mode. For other modes (100BASE-FX or 10BASE-T) the

proper value needs to be set via software or EEPROM.

Offset:

158h

Size:

32 bits

Bank:

Bits

Description

Type

Default

31:16

TX Latency (TX_LATENCY[15:0])

This field specifies the egress delay in nanoseconds between the PTP time-

stamp point and the network medium. The setting is used to adjust the inter-

nally captured 1588 clock value such that the resultant timestamp more

accurately corresponds to the start of the frame’s first symbol after the SFD

on the network medium.

The value depends on the port mode. Typical values are:

• 100BASE-TX: 95ns

• 100BASE-FX: 68ns plus the receive latency of the fiber transceiver

• 10BASE-T: 1139ns

Note:

The host S/W must not change this field while the 1588 Enable

(1588_ENABLE) bit in 1588 Command and Control Register

(1588_CMD_CTL) is set.

R/W

Note 2

15:0

RX Latency (RX_LATENCY[15:0])

This field specifies the ingress delay in nanoseconds between the network

medium and the PTP timestamp point. The setting is used to adjust the inter-

nally captured 1588 clock value such that the resultant timestamp more accu-

rately corresponds to the start of the frame’s first symbol after the SFD on the

network medium.

The value depends on the port mode. Typical values are:

• 100BASE-TX: 285ns

• 100BASE-FX: 231ns plus the receive latency of the fiber transceiver

• 10BASE-T: 1674ns

Note:

The host S/W must not change this field while the 1588 Enable

(1588_ENABLE) bit in 1588 Command and Control Register

(1588_CMD_CTL) is set.

R/W

285

Note 2

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