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LAN9250 Datasheet(PDF) 344 Page - Microchip Technology

Part # LAN9250
Description  Integrated Ethernet PHY with HP Auto-MDIX
PDF  421 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9250 Datasheet(HTML) 344 Page - Microchip Technology

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LAN9250
DS00001913A-page 344
 2015 Microchip Technology Inc.
14.8.22
1588 PORT RX PARSING CONFIGURATION REGISTER (1588_RX_PARSE_CONFIG)
This register is used to configure the PTP receive message detection.
Note:
Port and GPIO registers share a common address space. Port registers are selected by the Bank Select
(BANK_SEL[2:0] in the 1588 Bank Port GPIO Select Register (1588_BANK_PORT_GPIO_SEL).
Offset:
158h
Size:
32 bits
Bank:
1
Bits
Description
Type
Default
31:15
RESERVED
RO
-
14
RX Layer 2 Address 1 Enable (RX_LAYER2_ADD1_EN)
This bit enables the Layer 2 MAC address of 01:80:C2:00:00:0E for PTP
packets.
Note:
The host S/W must not change this bit while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
R/W
1b
13
RX Layer 2 Address 2 Enable (RX_LAYER2_ADD2_EN)
This bit enables the Layer 2 MAC address of 01:1B:19:00:00:00 for PTP
packets.
Note:
The host S/W must not change this bit while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
R/W
1b
12
RX Address 1 Enable (RX_ADD1_EN)
This bit enables the IPv4 MAC address of 01:00:5E:00:01:81 and IPv4 desti-
nation address of 224.0.1.129 for PTP packets.
This bit enables the IPv6 MAC address of 33:33:00:00:01:81 and IPv6 desti-
nation address of FF0X:0:0:0:0:0:0:181 for PTP packets.
Note:
The host S/W must not change this bit while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
R/W
1b
11
RX Address 2 Enable (RX_ADD2_EN)
This bit enables the IPv4 MAC address of 01:00:5E:00:01:82 and IPv4 desti-
nation address of 224.0.1.130 for PTP packets.
This bit enables the IPv6 MAC address of 33:33:00:00:01:82 and IPv6 desti-
nation address of FF0X:0:0:0:0:0:0:182 for PTP packets.
Note:
The host S/W must not change this bit while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
R/W
0b



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