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LAN9250 Datasheet(PDF) 342 Page - Microchip Technology

Part # LAN9250
Description  Integrated Ethernet PHY with HP Auto-MDIX
PDF  421 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9250 Datasheet(HTML) 342 Page - Microchip Technology

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LAN9250
DS00001913A-page 342
 2015 Microchip Technology Inc.
14.8.20
1588 PORT ASYMMETRY AND PEER DELAY REGISTER (1588_ASYM_PEERDLY)
Note:
Port and GPIO registers share a common address space. Port registers are selected by the Bank Select
(BANK_SEL[2:0] in the 1588 Bank Port GPIO Select Register (1588_BANK_PORT_GPIO_SEL).
Offset:
15Ch
Size:
32 bits
Bank:
0
Bits
Description
Type
Default
31:16
Port Delay Asymmetry (DELAY_ASYM[15:0])
This field specifies the previously known delay asymmetry in nanoseconds.
This is a signed 2’s complement number. Positive values occur when the
master-to-slave or responder-to-requestor propagation time is longer than
the slave-to-master or requestor-to-responder propagation time.
Note:
The host S/W must not change this field while the 1588 Enable
(1588_ENABLE) bit in 1588 Command and Control Register
(1588_CMD_CTL) is set.
R/W
0000h
15:0
RX Peer Delay (RX_PEER_DELAY[15:0])
This field specifies the measured peer delay in nanoseconds used during
peer-to-peer mode.
R/W
0000h



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