AD9694 datasheet(4/101 Pages) AD

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AD9694

Data Sheet

Rev. 0 | Page 4 of 101

SPECIFICATIONS

DC SPECIFICATIONS

AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V,

SPIVDD = 1.8 V, 500 MSPS, clock divider = 4, 1.8 V p-p full-scale differential input, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI

settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ)

range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C (TA = 25°C).

Table 1.

Parameter

Min

Typ

Max

Unit

RESOLUTION

Bits

ACCURACY

No Missing Codes

Guaranteed

Offset Error

% FSR

Offset Matching

% FSR

Gain Error

−5.0

+5.0

% FSR

Gain Matching

1.0

% FSR

Differential Nonlinearity (DNL)

−0.7

±0.4

+0.7

LSB

Integral Nonlinearity (INL)

−5.1

±1.0

+5.1

LSB

TEMPERATURE DRIFT

Offset Error

ppm/

°C

Gain Error

214

ppm/

°C

INTERNAL VOLTAGE REFERENCE

0.5

INPUT REFERRED NOISE

2.6

LSB rms

ANALOG INPUTS

Differential Input Voltage Range (Programmable)

1.44

1.80

2.16

V p-p

Common-Mode Voltage (VCM)

1.34

Differential Input Capacitance1

1.75

Differential Input Resistance

200

Ω

Analog Input Full Power Bandwidth

1.4

GHz

POWER SUPPLY

AVDD1

0.95

0.975

1.00

AVDD1_SR

0.95

0.975

1.00

AVDD2

1.71

1.8

1.89

AVDD3

2.44

2.5

2.56

DVDD

0.95

0.975

1.00

DRVDD1

0.95

0.975

1.00

DRVDD2

1.71

1.8

1.89

SPIVDD

1.71

1.8

1.89

IAVDD1

319

482

IAVDD1_SR

IAVDD2

438

473

IAVDD3

103

IDVDD2

121

180

IDRVDD11

162

207

IDRVDD21

ISPIVDD

1.6

POWER CONSUMPTION

Total Power Dissipation (Including Output Drivers)2

1.66

2.07

Power-Down Dissipation

325

Standby3

1.20

All lanes running. Power dissipation on DRVDD1 changes with lane rate and number of lanes used.

Full bandwidth mode.

Standby mode is controlled by the SPI.

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