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AD9694 Datasheet(PDF) 83 Page - Analog Devices |
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AD9694 Datasheet(HTML) 83 Page - Analog Devices |
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83 / 101 page  Data Sheet AD9694 Rev. 0 | Page 83 of 101 Addr Name Bits Bit Name Settings Description Reset Access 0x024C Channel map fast detect dwell time MSB [7:0] Fast detect dwell time, Bits[15:8] LSBs of fast detect dwell time counter target. This is a load value for a 16-bit counter that determines how long the ADC data must remain below the lower threshold before the FDDx pins are reset to 0. 0x0 R/W 0x026F Pair map signal monitor sync control [7:2] Reserved Reserved. 0x0 R 1 Reserved Reserved. 0x0 R/W 0 Signal monitor synchronization mode 0x0 R/W 0 Synchronization disabled. 1 Only the next valid edge of the SYSREF± pin is used to synchronize the signal monitor block. Subsequent edges of the SYSREF± pin are ignored. When the next SYSREF± is received, this bit is cleared. Note that the SYSREF± input pin must be enabled to synchronize the signal monitor blocks. 0x0270 Channel map signal monitor control [7:2] Reserved Reserved. 0x0 R 1 Peak detector 0x0 R/W 0 Peak detector disabled. 1 Peak detector enabled. 0 Reserved Reserved. 0x0 R 0x0271 Channel Map Signal Monitor Period 0 [7:0] Signal monitor period, Bits[7:0] This 24-bit value sets the number of output clock cycles over which the signal monitor performs its operation. Bit 0 is ignored. 0x80 R/W 0x0272 Channel Map Signal Monitor Period 1 [7:0] Signal monitor period, Bits[15:8] This 24-bit value sets the number of output clock cycles over which the signal monitor performs its operation. Bit 0 is ignored. 0x0 R/W 0x0273 Channel Map Signal Monitor Period 2 [7:0] Signal monitor period, Bits[23:16] This 24-bit value sets the number of output clock cycles over which the signal monitor performs its operation. Bit 0 is ignored. 0x0 R/W 0x0274 Channel map signal monitor status control [7:5] Reserved Reserved. 0x0 R 4 Result update 0x0 R/W 1 Status update based on Bits[2:0] (self clearing). 3 Reserved Reserved. 0x0 R [2:0] Result selection 0x1 R/W 001 Peak detector placed on status readback signals. 0x0275 Channel Map Signal Monitor Status 0 [7:0] Signal monitor result, Bits[7:0] Signal monitor status result. This 20-bit value contains the status result calculated by the signal monitor block. The content is dependent on the Register 0x0274, Bits[2:0] bit settings. 0x0 R 0x0276 Channel Map Signal Monitor Status 1 [7:0] Signal monitor result, Bits[15:8] Signal monitor status result. This 20-bit value contains the status result calculated by the signal monitor block. The content is dependent on the Register 0x0274, Bits[2:0] bit settings. 0x0 R |
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