AD9694 datasheet(24/101 Pages) AD

24 / 101 page

AD9694

Data Sheet

Rev. 0 | Page 24 of 101

Input Common Mode

The analog inputs of the AD9694 are internally biased to the

common mode as shown in Figure 57.

For dc-coupled applications, the recommended operation procedure

is to export the common-mode voltage to the VCM_CD/VREF

pin using the SPI writes listed in this section. The common-mode

voltage must be set by the exported value to ensure proper ADC

operation. Disconnect the internal common-mode buffer from

the analog input using Register 0x1908.

When performing SPI writes for dc coupling operation, use the

following register settings in order:

1. Set Register 0x1908, Bit 2 to 1 to disconnect the internal

common-mode buffer from the analog input.

2. Set Register 0x18A6 to 0x00 to turn off the voltage

reference.

3. Set Register 0x18E6 to 0x00 to turn off the temperature

diode export.

4. Set Register 0x18E0 to 0x04.

5. Set Register 0x18E1 to 0x1C.

6. Set Register 0x18E2 to 0x14.

7. Set Register 0x18E3, Bit 6 to 0x01 to turn on the VCM export.

8. Set Register 0x18E3, Bits[5:0] to the buffer current setting

(copy the buffer current setting from Register 0x1A4C and

mode export).

Analog Input Controls and SFDR Optimization

The AD9694 offers flexible controls for the analog inputs, such

as buffer current and input full-scale adjustment. All of the

available controls are shown in Figure 57.

AIN

CONTROL

(SPI)

10pF

VIN+x

100Ω

VIN–x

AVDD3

VCM

BUFFER

400Ω

100Ω

AVDD3

3.5pF

AVDD3

3.5pF

Figure 57. Analog Input Controls

Using Register 0x1A4C and Register 0x1A4D, , the buffer currents

on each channel can be scaled to optimize the SFDR over various

input frequencies and bandwidths of interest. As the input

buffer currents are set, the amount of current required by the

AVDD3 supply changes. This relationship is shown in Figure 58.

For a complete list of buffer current settings, see Table 38.

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0.16

0.18

0.20

100

150

200

250

300

350

400

450

500

550

600

BUFFER CURRENT SETTING (µA)

Figure 58. AVDD3 Power vs. Buffer Current Setting

In certain high frequency applications, the SFDR can be

improved by reducing the full-scale setting.

Table 11 shows the recommended buffer current settings for the

different analog input frequency ranges.

Table 11. SFDR Optimization for Input Frequencies

Nyquist Zone

Input Buffer Current Control

Setting, Register 0x1A4C and

First, Second, and Third

Nyquist

240 (Register 0x1A4C, Bits[5:0] =

Fourth Nyquist

400 (Register 0x1A4C, Bits[5:0] =

Absolute Maximum Input Swing

The absolute maximum input swing allowed at the inputs of the

AD9694 is 4.3 V p-p differential. Signals operating near or at

this level can cause permanent damage to the ADC.

VOLTAGE REFERENCE

A stable and accurate 0.5 V voltage reference is built into the

AD9694. This internal 0.5 V reference is used to set the full-

scale input range of the ADC. The full-scale input range can be

adjusted via the ADC function register (Register 0x1910). For

more information on adjusting the input swing, see Table 38.

Figure 59 shows the block diagram of the internal 0.5 V

reference controls.

ADC

CORE

FULL-SCALE

VOLTAGE

ADJUST

VREF PIN

CONTROL SPI

(0x18A6)

VREF

VIN–A/

VIN–B

VIN+A/

VIN+B

INTERNAL

VREF

GENERATOR

INPUT FULL-SCALE

RANGE ADJUST

SPI REGISTER

(0x1910)

Figure 59. Internal Reference Configuration and Controls

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