AD9694 datasheet(49/101 Pages) AD

49 / 101 page

Data Sheet

AD9694

Rev. 0 | Page 49 of 101

DIGITAL OUTPUTS

INTRODUCTION TO THE JESD204B INTERFACE

The AD9694 digital outputs are designed to the JEDEC

standard, JESD204B, serial interface for data converters.

JESD204B is a protocol to link the AD9694 to a digital

processing device over a serial interface with lane rates of up to

15 Gbps. The benefits of the JESD204B interface over LVDS

include a reduction in required board area for data interface

routing, and an ability to enable smaller packages for converter

and logic devices.

SETTING UP THE AD9694 DIGITAL INTERFACE

The following SPI writes are required for the AD9694 at startup

and each time the ADC is reset (datapath reset, soft reset, link

power-down/power-up, or hard reset):

1. Write 0x4F to Register 0x1228.

2. Write 0x0F to Register 0x1228.

3. Write 0x04 to Register 0x1222.

4. Write 0x00 to Register 0x1222.

5. Write 0x08 to Register 0x1262.

6. Write 0x00 to Register 0x1262.

The JESD204B data transmit blocks assemble the parallel data

from the ADC into frames and uses 8B/10B encoding as well as

optional scrambling to form serial output data. Lane synchron-

ization is supported through the use of special control characters

during the initial establishment of the link. Additional control

characters are embedded in the data stream to maintain synchroni-

zation thereafter. A JESD204B receiver is required to complete

the serial link. For additional details on the JESD204B interface,

refer to the JESD204B standard.

The JESD204B data transmit blocks in the AD9694 map up to

two physical ADCs or up to four virtual converters (when the

DDCs are enabled) over each of the two JESD204B links. Each

link can be configured to use one or two JESD204B lanes for up

to a total of four lanes for the AD9694 chip. The JESD204B

specification refers to a number of parameters to define the

link, and these parameters must match between the JESD204B

transmitter (the AD9694 output) and the JESD204B receiver

(the logic device input). The JESD204B outputs of the AD9694

function effectively as two individual JESD204B links. The two

JESD204B links can be synchronized if desired using the

SYSREF± input.

Each JESD204B link is described according to the following

parameters:

•

L = number of lanes per converter device (lanes per link)

(AD9694 value = 1 or 2)

•

M = number of converters per converter device (virtual

converters per link)

(AD9694 value = 1, 2, or 4)

•

F = octets per frame (AD9694 value = 1, 2, 4, or 8)

•

N΄ = number of bits per sample (JESD204B word size)

(AD9694 value = 8 or 16)

•

N = converter resolution

(AD9694 value = 7 to 16)

•

CS = number of control bits per sample

(AD9694 value = 0, 1, 2, or 3)

•

K = number of frames per multiframe

(AD9694 value = 4, 8, 12, 16, 20, 24, 28, or 32 )

•

S = samples transmitted per single converter per frame

cycle (AD9694 value = set automatically based on L, M, F,

and N΄)

•

HD = high density mode (AD9694 = set automatically based

on L, M, F, and N΄)

•

CF = number of control words per frame clock cycle per

converter device (AD9694 value = 0)

Figure 81 shows a simplified block diagram of the AD9694

JESD204B link. By default, the AD9694 is configured to use four

converters and four lanes. The Converter A and Converter B data

is output to SERDOUTAB0± and SERDOUTAB1±, and the

Converter C and Converter D data is output to SERDOUTCD0±

and SERDOUTCD1±. The AD9694 allows other configurations,

such as combining the outputs of each pair of converters into a

single lane, or changing the mapping of the digital output paths.

These modes are set up via a quick configuration register in the

SPI register map, along with additional customizable options.

By default in the AD9694, the 14-bit converter word from each

converter is broken into two octets (eight bits of data). Bit 13

(MSB) through Bit 6 are in the first octet. The second octet

contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits

can be configured as zeros or a pseudorandom number

sequence. The tail bits can also be replaced with control bits

indicating overrange, SYSREF±, or fast detect output. Control

bits are filled and inserted MSB first such that enabling CS = 1

activates Control Bit 2, enabling CS = 2 activates Control Bit 2

and Control Bit 1, and enabling CS = 3 activates Control Bit 2,

Control Bit 1, and Control Bit 0.

The two resulting octets can be scrambled. Scrambling is

optional; however, it is recommended to avoid spectral peaks

when transmitting similar digital data patterns. The scrambler

uses a self synchronizing, polynomial-based algorithm defined

by the equation 1 + x14 + x15. The descrambler in the receiver is

a self-synchronizing version of the scrambler polynomial.

The two octets are then encoded with an 8B/10B encoder. The

8B/10B encoder works by taking eight bits of data (an octet)

and encoding them into a 10-bit symbol. Figure 82 shows how

the 14-bit data is taken from the ADC, the tail bits are added,

the two octets are scrambled, and how the octets are encoded

into two 10-bit symbols. Figure 82 shows the default data format.

AD9694 Datasheet(PDF) 49 Page - Analog Devices

AD9694 Datasheet(HTML) 49 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL