AD9694 datasheet(28/101 Pages) AD

28 / 101 page

AD9694

Data Sheet

Rev. 0 | Page 28 of 101

ADC OVERRANGE AND FAST DETECT

In receiver applications, it is desirable to have a mechanism to

reliably determine when the converter is about to be clipped.

The standard overrange bit in the JESD204B outputs provides

information on the state of the analog input that is of limited

usefulness. Therefore, it is helpful to have a programmable

threshold below full scale that allows time to reduce the gain

before the clip actually occurs. In addition, because input

signals can have significant slew rates, the latency of this

function is of major concern. Highly pipelined converters can

have significant latency. The AD9694 contains fast detect

circuitry for individual channels to monitor the threshold and

to assert the FD_A, FD_B, FD_C, and FD_D pins.

ADC OVERRANGE

The ADC overrange indicator is asserted when an overrange is

detected on the input of the ADC. The overrange indicator can

be embedded within the JESD204B link as a control bit (when

CSB > 0). The latency of this overrange indicator matches the

sample latency.

FAST THRESHOLD DETECTION (FD_A, FD_B, FD_C,

AND FD_D)

The fast detect (FD) bits in Register 0x0040 are immediately set

whenever the absolute value of the input signal exceeds the

programmable upper threshold level. The FD bits are cleared

only when the absolute value of the input signal drops below the

lower threshold level for greater than the programmable dwell

time. This feature provides hysteresis and prevents the FD bits

from excessively toggling.

The operation of the upper threshold and lower threshold

registers, along with the dwell time registers, is shown in

Figure 67.

The FD indicator is asserted if the input magnitude exceeds the

value programmed in the fast detect upper threshold registers,

located at Register 0x0247 and Register 0x0248. The selected

threshold register is compared with the signal magnitude at the

output of the ADC. The fast upper threshold detection has a

latency of 30 clock cycles (maximum). The approximate upper

threshold magnitude is defined by

Upper Threshold Magnitude (dBFS) = 20log (Threshold

Magnitude/213)

The FD indicators are not cleared until the signal drops below

the lower threshold for the programmed dwell time. The lower

threshold is programmed in the fast detect lower threshold

registers, located at Register 0x0249 and Register 0x024A. The

fast detect lower threshold register is a 13-bit register that is

compared with the signal magnitude at the output of the ADC.

This comparison is subject to the ADC pipeline latency, but is

accurate in terms of converter resolution. The lower threshold

magnitude is defined by

Lower Threshold Magnitude (dBFS) = 20log (Threshold

Magnitude/213)

For example, to set an upper threshold of −6 dBFS, write 0xFFF

to Register 0x0247 and Register 0x0248. To set a lower threshold of

−10 dBFS, write 0xA1D to Register 0x0249 and Register 0x024A.

The dwell time can be programmed from 1 to 65,535 sample

clock cycles by placing the desired value in the fast detect dwell

time registers, located at Register 0x024B and Register 0x024C. See

the Memory Map section (Register 0x0040, and Register 0x0245 to

UPPER THRESHOLD

LOWER THRESHOLD

FD_A OR FD_B

DWELL TIME

TIMER RESET BY

RISE ABOVE

LOWER

THRESHOLD

TIMER COMPLETES BEFORE

SIGNAL RISES ABOVE

LOWER THRESHOLD

DWELL TIME

Figure 67. Threshold Settings for the FD_A and FD_B Signals

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