AD9694 datasheet(77/101 Pages) AD

77 / 101 page

Data Sheet

AD9694

Rev. 0 | Page 77 of 101

Addr

Name

Bits

Bit Name

Settings Description

Reset Access

0x003F

Channel map

chip power-

down pin

PDWN/STBY disable

Used in conjunction with Register 0x0040.

0x0

R/W

Power-down pin (PDWN/STBY) enabled.

Global pin control selection enabled (default).

Power-down pin (PDWN/STBY)

disabled/ignored. Global pin control selection

ignored.

[6:0]

Reserved

Reserved.

0x0

0x0040

Pair Map Chip

Pin Control 1

[7:6]

PDWN/STBY function

0x0

R/W

Power-down pin. Assertion of the external

power-down pin (PDWN/STBY) causes the chip

to enter full power-down mode.

Standby pin. Assertion of the external power-

down (PDWN/STBY) causes the chip to enter

standby mode.

Pin disabled. Assertion of the external power-

down pin (PDWN/STBY) is ignored.

[5:3]

Fast Detect B/D

(FD_B/FD_D)

0x7

R/W

000

Fast Detect B/D output.

001

JESD204B LMFC output.

010

JESD204B internal SYNC~ output.

111

Disabled (configured as input with weak pull-

down).

[2:0]

Fast Detect A/C

(FD_A/FD_C)

0x7

R/W

000

Fast Detect A/C output.

001

JESD204B LMFC output.

010

JESD204B internal SYNC~ output.

111

Disabled (configured as input with weak pull-

down).

0x0108

Pair map

clock divider

control

[7:3]

Reserved

Reserved.

0x0

[2:0]

Clock divider

0x1

R/W

000

Divide by 1.

001

Divide by 2.

011

Divide by 4.

111

Divide by 8.

0x0109

Channel map

clock divider

phase

[7:4]

Reserved

Reserved.

0x0

[3:0]

Clock divider phase

offset

0x0

R/W

0000

0 input clock cycles delayed.

0001

1/2 input clock cycles delayed (invert clock).

0010

1 input clock cycle delayed.

0011

1 1/2 input clock cycles delayed.

0100

2 input clock cycles delayed.

0101

21/2 input clock cycles delayed.

0110

3 input clock cycles delayed.

0111

31/2 input clock cycles delayed.

AD9694 Datasheet(PDF) 77 Page - Analog Devices

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