AD9694 datasheet(41/101 Pages) AD

41 / 101 page

Data Sheet

AD9694

Rev. 0 | Page 41 of 101

FIR FILTERS

OVERVIEW

Four sets of decimate by 2, low-pass, half-band, finite impulse

response (FIR) filters (labeled HB1 FIR, HB2 FIR, HB3 FIR,

and HB4 FIR in Figure 72) follow the frequency translation

stage. After the carrier of interest is tuned down to dc (carrier

frequency = 0 Hz), these filters efficiently lower the sample rate,

while providing sufficient alias rejection from unwanted

adjacent carriers around the bandwidth of interest.

HB1 FIR is always enabled and cannot be bypassed. The HB2,

HB3, and HB4 FIR filters are optional and can be bypassed for

higher output sample rates.

Table 18 shows the different bandwidths selectable by including

different half-band filters. In all cases, the DDC filtering stage

on the AD9694 provides <−0.001 dB of pass-band ripple and

>100 dB of stop band alias rejection.

Table 19 shows the amount of stop band alias rejection for

multiple pass-band ripple/cutoff points. The decimation ratio of

the filtering stage of each DDC can be controlled individually

through Bits[1:0] of the DDC control registers (Register 0x0310

and Register 0x0330) in conjunction with the pair index register

(Register 0x0009).

Table 18. DDC Filter Characteristics

Half-Band

Filter

Selection

Real Output

Complex (I/Q) Output

Alias

Protected

Bandwidth

(MHz)

Ideal SNR

Improvement1

(dB)

Pass-

Band

Ripple

(dB)

Alias

Rejection

(dB)

Decimation

Ratio

Output

Sample

Rate

(MSPS)

Decimation

Ratio

Output Sample

Rate (MSPS)

HB1

500

250 (I) + 250 (Q)

200

<−0.0001

>100

HB1 + HB2

250

125 (I) + 125 (Q)

100

HB1 + HB2 +

HB3

125

62.5 (I) + 62.5 (Q)

HB1 + HB2 +

HB3 + HB4

62.5

31.25 (I) + 31.25 (Q)

Ideal SNR improvement due to oversampling and filtering = 10log(bandwidth/(fS/2)).

Table 19. DDC Filter Alias Rejection

Alias Rejection

(dB)

Pass-Band Ripple/Cutoff

Point (dB)

Alias Protected Bandwidth for Real

(I) Outputs1

Alias Protected Bandwidth for Complex

(I/Q) Outputs

>100

<−0.0001

<40% × fOUT

<80% × fOUT

<−0.0002

<40.12% × fOUT

<80.12% × fOUT

<−0.0003

<40.23% × fOUT

<80.46% × fOUT

<−0.0005

<40.36% × fOUT

<80.72% × fOUT

<−0.0009

<40.53% × fOUT

<81.06% × fOUT

25.07

−0.5

45.17% × fOUT

90.34% × fOUT

19.3

−1.0

46.2% × fOUT

92.4% × fOUT

10.7

−3.0

48.29% × fOUT

96.58% × fOUT

fOUT = ADC input sample rate ÷ DDC decimation.

AD9694 Datasheet(PDF) 41 Page - Analog Devices

AD9694 Datasheet(HTML) 41 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL