AD9694 datasheet(68/101 Pages) AD

68 / 101 page

AD9694

Data Sheet

Rev. 0 | Page 68 of 101

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit locations.

The memory map is divided into four sections: the Analog Devices

SPI registers (Register 0x0000 to Register 0x000D and Register

0x18A6 to Register 0x1A4C), the ADC function registers

(Register 0x003F to Register 0x027A), the DDC function registers

(Register 0x0300 to Register 0x0347), and the digital outputs

and test modes registers (Register 0x0550 to Register 0x05C0).

Table 38 (see the Memory Map section) documents the default

hexadecimal value for each hexadecimal address shown. The

column with the heading Bit 7 (MSB) is the start of the default

hexadecimal value given. For example, Address 0x0561, the

output mode register, has a hexadecimal default value of 0x01.

This default value means that Bit 0 = 1, and the remaining bits

are 0s. This setting is the default output format value, which is

twos complement. For more information on this function and

others, see the Table 38.

Unassigned and Reserved Locations

All address and bit locations that are not included in Table 38

are not currently supported for this device. Write unused bits of

a valid address location with 0s unless the default value is set

otherwise. Writing to these locations is required only when part

of an address location is unassigned (for example, Address 0x0561).

If the entire address location is open (for example, Address 0x0013),

do not write to this address location.

Default Values

After the AD9694 is reset, critical registers are loaded with

default values. The default values for the registers are given in

the memory map register table, Table 38.

Logic Levels

An explanation of logic level terminology follows:

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

•

X denotes a don’t care bit.

ADC Pair Addressing

The AD9694 functionally operates as two pairs of dual IF

receiver channels. There are two ADCs and two DDCs in each

pair making for a total of four of each for the AD9694 device.

To access the SPI registers for each pair, the pair index must be

written in Register 0x0009. The pair index register must be

written prior to any other SPI write to the AD9694.

Channel Specific Registers

Some channel setup functions, such as the fast detect control

(Register 0x0247), can be programmed to a different value for

each channel. In these cases, channel address locations are

internally duplicated for each channel. These registers and bits

are designated in Table 38 as local. These local registers and bits

can be accessed by setting the appropriate Channel A/Channel C

or Channel B/Channel D bits in Register 0x0008. The particular

channel that is addressed is dependent upon the pair selection

written to Register 0x0009. If both bits are set, the subsequent

write affects the registers of both channels. In a read cycle, set

only Channel A/Channel C or Channel B/ Channel D to read

one of the two registers. If both bits are set during an SPI read

cycle, the device returns the value for Channel A. If both pairs

and both channels are selected via Register 0x0009 and Register

0x0008, the device returns the value for Channel A.

The names of the registers listed in Table 38 and Table 39 are

prefixed with either global map, channel map, JESD204B map,

or pair map. Registers in the pair map and JESD204B map are

apply to a pair of channels, either Pair A/B or Pair C/D. To write

registers in the pair map and JESD204B map, the pair index register

(Register 0x0009) must be written to address the appropriate pair.

The SPI Configuration A (Register 0x0000), SPI Configuration B

(Register 0x0001), and pair index (Register 0x0009) registers are

the only registers that reside in the global map. Registers in the

channel map are local to each channel, either Channel A,

Channel B, Channel C, or Channel D. To write registers in the

channel map, the pair index register (Register 0x0009) must be

written first to address the desired pair (Pair A/B or Pair C/D)

followed by writing the channel index register (Register 0x0008)

to select the desired channel (Channel A/ Channel C or

Channel B/Channel D).

For example, to write Channel A to test mode (set by Register

0x0550), first write 0x01 to Register 0x0009 to select Pair A/B,

followed by writing 0x01 to Register 0x0008 to select Channel A.

Then, write Register 0x0550 to the value for the desired test mode.

To write all channels to a test mode (set by Register 0x0550),

first write Register 0x0009 to a value of 0x03 to select both Pair

A/B and Pair C/D, followed by writing Register 0x0008 to a value

of 0x03 to select Channel A, Channel B, Channel C, and Channel

D. Next, write Register 0x0550 to the value for the desired test

mode.

SPI Soft Reset

After issuing a soft reset by programming 0x81 to

programming the AD9694 for application setup, ensure that an

adequate delay is programmed into the firmware after asserting

the soft reset and before starting the device setup.

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