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AD9694 Datasheet(PDF) 97 Page - Analog Devices

Part # AD9694
Description  14-Bit, 500 MSPS JESD204B, Quad Analog-to-Digital Converter
PDF  101 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9694 Datasheet(HTML) 97 Page - Analog Devices

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Data Sheet
AD9694
Rev. 0 | Page 97 of 101
Addr
Name
Bits
Bit Name
Settings Description
Reset Access
0x05B3
JESD204B
map JTX lane
Assignment 2
7
Reserved
Reserved.
0x0
R
[6:4]
Reserved
Reserved.
0x1
R/W
3
Reserved
Reserved.
0x0
R
[2:0]
SERDOUTx1± lane
assignment
0x1
R/W
0
Logical Lane 0.
1
Logical Lane 1 (default).
10
Logical Lane 2.
11
Logical Lane 3.
0x05C0
JESD204B
map
JESD204B
serializer
drive adjust
7
Reserved
Reserved.
0x0
R
[6:4]
Swing voltage
SERDOUTx1±
0
1.0 × DRVDD1 (differential).
0x1
R/W
1
0.850 × DRVDD1 (differential).
3
Reserved
Reserved.
0x0
R
[2:0]
Swing voltage
SERDOUTx0±
0
1.0 × DRVDD1 (differential).
0x1
R/W
1
0.850 × DRVDD1 (differential).
0x05C4
JESD204B
serializer
preemphasis
selection
register for
Logical
Lane 0
7
Post tap polarity
0
Normal.
0x0
R/W
1
Inverted.
[6:4]
Sets post tab level
0
0 dB
0x0
R/W
1
3 dB.
10
6 dB.
11
9 dB.
100
12 dB.
101
Not valid.
110
Not valid.
111
Not valid.
3
Pre tab polarty
0
Normal.
0x0
R/W
1
Inverted.
[2:0]
Sets pre tab level
0
0 dB.
0x0
R/W
1
3 dB.
10
6 dB.
11
9 dB.
100
12 dB.
101
Not valid.
110
Not valid.
111
Not valid.
0x05C6
JESD204B
serializer
preemphasis
selection
register for
Logical
Lane 1
7
Post tap polarity
0
Normal
0x0
R/W
1
Inverted
[6:4]
Sets post tab level
0x0
R/W
0
0 dB.
1
3 dB.
10
6 dB.
11
9 dB.
100
12 dB.
101
Not valid.
110
Not valid.
111
Not valid.



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