AD9694 datasheet(23/101 Pages) AD

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Data Sheet

AD9694

Rev. 0 | Page 23 of 101

THEORY OF OPERATION

ADC ARCHITECTURE

The architecture of the AD9694 consists of an input buffered

pipelined ADC. The input buffer is designed to provide a 200 Ω

termination impedance to the analog input signal. The

equivalent circuit diagram of the analog input termination is

shown in Figure 44.

The input buffer provides a linear high input impedance (for

ease of drive) and reduces kickback from the ADC. The buffer

is optimized for high linearity, low noise, and low power. The

quantized outputs from each stage are combined into a final

14-bit result in the digital correction logic. The pipelined

architecture permits the first stage to operate with a new input

sample while at the same time, the remaining stages operate

with the preceding samples. Sampling occurs on the rising edge

of the clock.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9694 is a differential buffer with an

internal common-mode voltage of 1.35 V. The clock signal

alternately switches the input circuit between sample mode and

hold mode. Either a differential capacitor or two single-ended

capacitors can be placed on the inputs to provide a matching

passive network. This configuration ultimately creates a low-pass

filter at the input, which limits unwanted broadband noise. See

Figure 74 and Figure 75 for details on input network

recommendations.

For best dynamic performance, the source impedances driving

VIN+x and VIN−x must be matched such that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC. An internal reference

buffer creates a differential reference that defines the span of the

ADC core.

Maximum SNR performance is achieved by setting the ADC to

the largest span in a differential configuration. In the case of the

AD9694, the available span is programmable through the SPI

port from 1.44 V p-p to 2.16 V p-p differential, with 1.80 V p-p

differential being the default.

Dither

The AD9694 has internal on-chip dither circuitry that improves

the ADC linearity and SFDR particularly at smaller signal

levels. A known but random amount of white noise is injected

into the input of the AD9694. This dither improves the small

signal linearity within the ADC transfer function and is precisely

subtracted out digitally. The dither is turned on by default and

does not reduce the ADC input dynamic range. The data sheet

specifications and limits are obtained with the dither turned on.

The dither can be disabled using SPI writes to Register 0x0922.

Disabling the dither can slightly improve the SNR (by about 0.2 dB)

at the expense of the small signal SFDR.

Differential Input Configurations

There are several ways to drive the AD9694, either actively or

passively. However, optimum performance is achieved by

driving the analog input differentially.

For applications where SNR and SFDR are key parameters,

differential transformer coupling is the recommended input

configuration (see Figure 55 and Figure 56) because the noise

performance of most amplifiers is not adequate to achieve the

true performance of the AD9694.

For low to midrange frequencies, a double balun or double

transformer network (see Figure 55) is recommended for

optimum performance of the AD9694. For higher frequencies

in the second or third Nyquist zones, it is better to remove some

of the front-end passive components to ensure wideband

operation (see Figure 56).

10Ω

0.1µF

VIN+x

VIN–x

0.1µF

BALUN

50Ω

AGND

10Ω

50Ω

10Ω

0Ω

2pF

10Ω

0Ω

Figure 55. Differential Transformer Coupled Configuration for First and

Second Nyquist Frequencies

10Ω

0.1µF

VIN+x

VIN–x

0.1µF

50Ω

AGND

DNI

50Ω

DNI

10Ω

0Ω

DNI

10Ω

0Ω

BALUN

Figure 56. Differential Transformer Coupled Configuration for Third and

Fourth Nyquist Zones

AD9694 Datasheet(PDF) 23 Page - Analog Devices

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