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AD9694 Datasheet(PDF) 73 Page - Analog Devices

Part # AD9694
Description  14-Bit, 500 MSPS JESD204B, Quad Analog-to-Digital Converter
PDF  101 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9694 Datasheet(HTML) 73 Page - Analog Devices

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Data Sheet
AD9694
Rev. 0 | Page 73 of 101
Reg.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RW
0x056E
JESD204B map
PLL control
JESD204B lane rate control
Reserved
0x00
R/W
0x056F
JESD204B map
PLL status
PLL lock
status
Reserved
Reserved
Reserved
0x00
R
0x0570
JESD204B map
JTX quick
configuration
Quick Configuration L
Quick Configuration M
Quick Configuration F
0x49
R/W
0x0571
JESD204B map
JTX Link
Control 1
Standby
mode
Tail bit (t)
PN
Long
transport
layer test
Lane syn-
chronization
ILAS sequence mode
FACI
Link
control
0x14
R/W
0x0572
JESD204B map
JTX Link
Control 2
SYNCINB±x pin control
SYNCINB±x
pin invert
SYNCINB±x
pin type
Reserved
8B/10B
bypass
8B/10B bit
invert
Reserved
0x00
R/W
0x0573
JESD204B map
JTX Link
Control 3
Checksum mode
Test injection point
JESD204B test mode patterns
0x00
R/W
0x0574
JESD204B map
JTX Link
Control 4
ILAS delay
Reserved
Link layer test mode
0x00
R/W
0x0578
JESD204B map
JTX LMFC offset
Reserved
LMFC phase offset value
0x00
R/W
0x0580
JESD204B map
JTX DID
configuration
JESD204B Tx DID value
0x00
R/W
0x0581
JESD204B map
JTX BID
configuration
Reserved
JESD204B Tx BID value
0x00
R/W
0x0583
JESD204B map
JTX LID 0
configuration
Reserved
Lane 0 LID value
0x00
R/W
0x0585
JESD204B map
JTX LID 1
configuration
Reserved
Lane 1 LID value
0x02
R/W
0x058B
JESD204B map
JTX SCR L
configuration
JESD204B
scrambling
(SCR)
Reserved
JESD204B lanes (L)
0x81
R/W
0x058C
JESD204B map
JTX F
configuration
Number of octets per frame (F)
0x01
R
0x058D
JESD204B map
JTX K
configuration
Reserved
Number of frames per multiframe (K)
0x1F
R/W
0x058E
JESD204B map
JTX M
configuration
Number of converters per link
0x01
R
0x058F
JESD204B map
JTX CS N
configuration
Number of control bits (CS)
per sample
Reserved
ADC converter resolution (N)
0x0F
R/W
0x0590
JESD204B map
JTX Subclass
Version NP
configuration
Subclass support
ADC number of bits per sample (N')
0x2F
R/W
0x0591
JESD204B map
JTX JV S
configuration
Reserved
Samples per converter frame cycle (S)
0x20
R
0x0592
JESD204B map
JTX HD CF
configuration
HD value
Reserved
Control words per frame clock cycle per link (CF)
0x00
R
0x05A0
JESD204B map
JTX Checksum
0 configuration
Checksum 0 checksum value for SERDOUTx0±
0xC3
R
0x05A1
JESD204B map
JTX Checksum
1 configuration
Checksum 1 checksum value for SERDOUTx1±
0xC4
R
0x05B0
JESD204B map
JTX lane
power-down
Reserved
Reserved
Reserved
Reserved
Reserved
JESD204B
Lane 1
power-
down
Reserved
JESD204B
Lane 0
power-
down
0xFA
R/W



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