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AD9694 Datasheet(PDF) 69 Page - Analog Devices |
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AD9694 Datasheet(HTML) 69 Page - Analog Devices |
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69 / 101 page  Data Sheet AD9694 Rev. 0 | Page 69 of 101 MEMORY MAP REGISTER TABLE SUMMARY All address locations that are not included in Table 38 are not currently supported for this device and must not be written. Table 38. Memory Map Summary Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x0000 Global Map SPI Configuration A Soft reset (self clearing) LSB first mirror Address ascension mirror Reserved Reserved Address ascension LSB first Soft reset (self clearing) 0x00 R/W 0x0001 Global Map SPI Configuration B Single instruction Reserved Datapath soft reset (self clearing) Reserved 0x00 R/W 0x0002 Channel map chip config- uration Reserved Channel power modes 0x00 R/W 0x0003 Pair map chip type CHIP_TYPE 0x03 R 0x0004 Pair map chip ID LSB CHIP_ID 0xDB R 0x0006 Pair map chip grade CHIP_SPEED_GRADE Reserved 0x00 R 0x0008 Pair map device index Reserved Channel B/D Channel A/ C 0x03 R/W 0x0009 Global map pair index Reserved Pair C/D Pair A/B 0x03 R/W 0x000A Pair map scratch pad Scratch pad 0x07 R/W 0x000B Pair map SPI revision SPI_REVISION 0x01 R 0x000C Pair map vendor ID LSB CHIP_VENDOR_ID[7:0] 0x56 R 0x000D Pair map vendor ID MSB CHIP_VENDOR_ID[15:8] 0x04 R 0x003F Channel map chip power- down pin PDWN/STBY disable Reserved 0x00 R/W 0x0040 Pair Map Chip Pin Control 1 PDWN/STBY function Fast Detect B/D (FD_B/FD_D) Fast Detect A/C (FD_A/FD_C) 0x3F R/W 0x0108 Pair map clock divider control Reserved Clock divider 0x01 R/W 0x0109 Channel map clock divider phase Reserved Clock divider phase offset 0x00 R/W 0x010A Pair map clock divider SYSREF control Clock divider autophase adjust Reserved Clock divider negative skew window Clock divider positive skew window 0x00 R/W 0x0110 Pair map clock delay control Reserved Clock delay mode select 0x00 R/W 0x0111 Channel map clock super fine delay Clock super fine delay adjust 0x00 R/W 0x0112 Channel map clock fine delay Clock fine delay adjust 0xC0 R/W 0x011A Clock detection control Reserved Clock detection threshold Clock detection enable Reserved 0x00 R/W 0x011B Pair map clock status Reserved Input clock detect 0x00 R 0x0120 Pair Map SYSREF Control 1 Reserved SYSREF± flag reset Reserved SYSREF± transition select CLK± edge select SYSREF± mode select Reserved 0x00 R/W 0x0121 Pair Map SYSREF Control 2 Reserved SYSREF± N shot ignore counter select 0x00 R/W |
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