 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD9694 Datasheet(PDF) 1 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9694 Datasheet(HTML) 1 Page - Analog Devices |
|
|
1 / 101 page  14-Bit, 500 MSPS JESD204B, Quad Analog-to-Digital Converter Data Sheet AD9694 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 15 Gbps 1.66 W total power at 500 MSPS 415 mW per analog-to-digital converter (ADC) channel SFDR = 82 dBFS at 305 MHz (1.80 V p-p input range) SNR = 66.8 dBFS at 305 MHz (1.80 V p-p input range) Noise density = −151.5 dBFS/Hz (1.80 V p-p input range) 0.975 V, 1.8 V, and 2.5 V dc supply operation No missing codes Internal ADC voltage reference Analog input buffer On-chip dithering to improve small signal linearity Flexible differential input range 1.44 V p-p to 2.16 V p-p (1.80 V p-p nominal) 1.4 GHz analog input full power bandwidth Amplitude detect bits for efficient AGC implementation 4 integrated wideband digital processors 48-bit NCO, up to 4 cascaded half-band filters Differential clock input Integer clock divide by 1, 2, 4, or 8 On-chip temperature diode Flexible JESD204B lane configurations APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, W-CDMA, GSM, LTE, LTE-A General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) FUNCTIONAL BLOCK DIAGRAM SDIO SCLK CSB AGND AD9694 SERDOUT0AB± SYSREF± 14 SPI CONTROL 14 2 PDWN/STBY JESD204B SUBCLASS 1 CONTROL FAST DETECT SERDOUT1AB± VIN+B VIN–B ADC CORE ADC CORE SIGNAL MONITOR SYNCINB±AB VIN+C VIN–C FD_C FD_D SERDOUT0CD± SERDOUT1CD± VIN+D VIN–D Tx OUTPUTS JESD204B HIGH-SPEED SERIALIZER SYNCINB±CD AVDD1 (0.975V) AVDD2 (1.8V) DRVDD (0.975V) DVDD (0.975V) AVDD3 (2.5V) AVDD1_SR (0.975V) SPIVDD (1.8V) DRVDD2 (1.8V) DIGITAL DOWN CONVERTER (DDC) DIGITAL DOWN CONVERTER (DDC) 2 Tx OUTPUTS JESD204B HIGH-SPEED SERIALIZER VIN+A VIN–A FD_A FD_B 14 14 FAST DETECT ADC CORE ADC CORE SIGNAL MONITOR DIGITAL DOWN CONVERTER (DDC) DIGITAL DOWN CONVERTER (DDC) SIGNAL MONITOR AND FAST DETECT CLK+ CLK– CLOCK GENERATION ÷2 ÷4 ÷8 BUFFER BUFFER BUFFER BUFFER DRGND VCM_AB VCM_CD Figure 1. |
Similar Part No. - AD9694 |
|
Similar Description - AD9694 |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
