AD9694 datasheet(78/101 Pages) AD

78 / 101 page

AD9694

Data Sheet

Rev. 0 | Page 78 of 101

Addr

Name

Bits

Bit Name

Settings Description

Reset Access

1000

4 input clock cycles delayed.

1001

41/2 input clock cycles delayed.

1010

5 input clock cycles delayed.

1011

51/2 input clock cycles delayed.

1100

6 input clock cycles delayed.

1101

61/2 input clock cycles delayed.

1110

7 input clock cycles delayed.

1111

7 1/2 input clock cycles delayed.

0x010A

Pair map

clock diviver

SYSREF

control

Clock divider autophase

adjust

0x0

R/W

Clock divider phase is not changed by SYSREF

(disabled).

Clock divider phase is automatically adjusted

by SYSREF (enabled).

[6:4]

Reserved

Reserved.

0x0

[3:2]

Clock divider negative

skew window

0x0

R/W

No negative skew: SYSREF must be captured

accurately.

1/2 device clocks of negative skew.

1 device clock of negative skew.

1 1/2 device clocks of negative skew.

[1:0]

Clock divider positive

skew window

0x0

R/W

No positive skew: SYSREF must be captured

accurately.

1/2 device clocks of positive skew.

1 device clock of positive skew.

1 1/2 device clocks of positive skew

0x0110

Pair map

clock delay

control

[7:3]

Reserved

Reserved.

0x0

[2:0]

Clock delay mode select

Clock delay mode select. Used in conjunction

with Register 0x0111 and Register 0x0112.

0x0

R/W

000

No clock delay.

001

Reserved.

010

Fine delay: only Delay Step 0 to Delay Step 16

valid.

011

Fine delay (lowest jitter): only Delay Step 0 to

Delay Step 16 valid.

100

Fine delay: all 192 delay steps valid.

101

Reserved (same as 100).

110

Fine delay enabled (all 192 delay steps valid);

super fine delay enabled (all 128 delay steps

valid).

AD9694 Datasheet(PDF) 78 Page - Analog Devices

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