AD9694 datasheet(79/101 Pages) AD

79 / 101 page

Data Sheet

AD9694

Rev. 0 | Page 79 of 101

Addr

Name

Bits

Bit Name

Settings Description

Reset Access

0x0111

Channel map

clock

superfine

delay

[7:0]

Clock super fine delay

adjust

Clock super fine delay adjust: this is an

unsigned control to adjust the super fine

sample clock delay in 0.25 ps steps.

0x0

R/W

0x00 = 0 delay steps.

…

0x08 = 8 delay steps.

…

0x80 = 128 delay steps.

0x0112

Channel map

clock fine

delay

[7:0]

Clock fine delay adjust

Clock fine delay adjust: this is an unsigned

control to adjust the fine sample clock skew in

1.725 ps steps.

0xC0

R/W

0x00 = 0 delay steps.

…

0x08 = 8 delay steps.

…

0xC0 = 192 delay steps.

0x011A

Clock

detection

control

[7:5]

Reserved

Reserved.

0x0

R/W

[4:3]

Clock detection

threshold

Clock detection threshold.

0x1

R/W

200 MHz.

150 MHz.

Clock detection enable

0x1

R/W

Enable.

Disable.

0x011B

Pair map

clock status

[7:1]

Reserved

Reserved.

0x0

Input clock detect

Clock detection status

0x0

Input clock not detected.

Input clock detected/locked.

0x011C

Clock DCS

control

[7:3]

Reserved

0x1

R/W

Clock DCS enable

DCS bypassed.

0x0

R/W

DCS enabled.

Clock DCS power-up

DCS powered down

0x0

R/W

DCS powered up. The DCS must be powered

up before being enabled.

0x0120

Pair map

SYSREF

Control 1

Reserved

Reserved.

0x0

SYSREF± flag reset

0x0

R/W

Normal flag operation.

SYSREF flags held in reset (setup/hold error

flags cleared).

Reserved

Reserved.

0x0

AD9694 Datasheet(PDF) 79 Page - Analog Devices

AD9694 Datasheet(HTML) 79 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL