AD9694 datasheet(9/101 Pages) AD

9 / 101 page

Data Sheet

AD9694

Rev. 0 | Page 9 of 101

Parameter

Min

Typ

Max

Unit

LATENCY5

Pipeline Latency

Sample clock cycles

Fast Detect Latency

Sample clock cycles

APERTURE

Aperture Delay (tA)

160

Aperture Uncertainty (Jitter, tj)

fs rms

Out of Range Recovery Time

Sample clock cycles

1 The maximum sample rate is the clock rate after the divider.

2 The minimum sample rate operates at 240 MSPS with L = 2 or L = 1. See SPI Register 0x011A to reduce the threshold of the clock detect circuit.

3 Baud rate = 1/UI. A subset of this range can be supported.

4 Default L = 2 for each link. This number can be changed based on the sample rate and decimation ratio.

5 No DDCs used. L = 2, M = 2, F = 2 for each link.

TIMING SPECIFICATIONS

Table 7.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

CLK+ to SYSREF+ TIMING REQUIREMENTS

See Figure 3

tSU_SR

Device clock to SYSREF+ setup time

−44.8

tH_SR

Device clock to SYSREF+ hold time

64.4

SPI TIMING REQUIREMENTS

See Figure 4

tDS

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHIGH

Minimum period that SCLK must be in a logic high state

tLOW

Minimum period that SCLK must be in a logic low state

tACCESS

Maximum time delay between falling edge of SCLK and output

data valid for a read operation

tDIS_SDIO

Time required for the SDIO pin to switch from an output to an

input relative to the CSB rising edge (not shown in Figure 4)

Timing Diagrams

N – 53

N – 52

N – 51

N – 50

N – 1

SAMPLE N

N + 1

APERTURE

DELAY

N – 54

CLK+

CLK–

ANALOG

INPUT

SIGNAL

Figure 2. Data Output Timing (Full Bandwidth Mode; L = 4; M = 2; F = 1)

CLK+

CLK–

SYSREF+

SYSREF–

tSU_SR

tH_SR

Figure 3. SYSREF± Setup and Hold Timing

AD9694 Datasheet(PDF) 9 Page - Analog Devices

AD9694 Datasheet(HTML) 9 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL