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AD9694 Datasheet(PDF) 71 Page - Analog Devices |
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AD9694 Datasheet(HTML) 71 Page - Analog Devices |
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71 / 101 page ![]() Data Sheet AD9694 Rev. 0 | Page 71 of 101 Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x0275 Channel Map Signal Monitor Status 0 Signal monitor result, Bits[7:0] 0x00 R 0x0276 Channel Map Signal Monitor Status 1 Signal monitor result, Bits[15:8] 0x00 R 0x0277 Channel Map Signal Monitor Status 2 Reserved Signal monitor result, Bits[19:16] 0x00 R 0x0278 Channel map signal monitor status frame counter Period count result, Bits[7:0] 0x00 R 0x0279 Channel map signal monitor serial framer control Reserved Reserved Signal monitor SPORT over JESD204B enable 0x00 R/W 0x027A Channel map signal monitor serial framer input selection Reserved Signal monitor SPORT over JESD204B peak detector enable 0x02 R/W 0x0300 Pair Map DDC sync control Reserved Reserved Reserved DDC NCO soft reset Reserved DDC next sync DDC synchroni- zation mode 0x00 R/W 0x0310 Pair Map DDC 0 control DDC 0 mixer select DDC 0 gain select DDC 0 IF (intermediate frequency) mode DDC 0 complex to real enable Reserved DDC 0 decimation rate select 0x00 R/W 0x0311 Pair Map DDC 0 input select Reserved DDC 0 Q input select Reserved DDC 0 I input select 0x00 R/W 0x0314 Pair Map DDC 0 Phase Increment 0 DDC 0 NCO frequency value, twos complement, Bits[7:0] 0x00 R/W 0x0315 Pair Map DDC 0 Phase Increment 1 DDC 0 NCO frequency value, twos complement, Bits[15:8] 0x00 R/W 0x0316 Pair Map DDC 0 Phase Increment 2 DDC 0 NCO frequency value, twos complement, Bits[23:16] 0x00 R/W 0x0317 Pair Map DDC 0 Phase Increment 3 DDC 0 NCO frequency value, twos complement, Bits[31:24] 0x00 R/W 0x0318 Pair Map DDC 0 Phase Increment 4 DDC 0 NCO frequency value, twos complement, Bits[39:32] 0x00 R/W 0x031A Pair Map DDC 0 Phase Increment 5 DDC 0 NCO frequency value, twos complement, Bits[47:40] 0x00 R/W 0x031D Pair Map DDC 0 Phase Offset 0 DDC 0 NCO phase value, twos complement, Bits[7:0] 0x00 R/W 0x031E Pair Map DDC 0 Phase Offset 1 DDC 0 NCO phase value, twos complement, Bits[15:8] 0x00 R/W 0x031F Pair Map DDC 0 Phase Offset 2 DDC 0 NCO phase value, twos complement, Bits[23:16] 0x00 R/W 0x0320 Pair Map DDC 0 Phase Offset 3 DDC 0 NCO phase value, twos complement, Bits[31:24] 0x00 R/W 0x0321 Pair Map DDC 0 Phase Offset 4 DDC 0 NCO phase value, twos complement, Bits[39:32] 0x00 R/W 0x0322 Pair Map DDC 0 Phase Offset 5 DDC 0 NCO phase value, twos complement, Bits[47:40] 0x00 R/W 0x0327 Pair Map DDC 0 test enable Reserved DDC 0 Q output test mode enable Reserved DDC 0 I output test mode enable 0x00 R/W 0x0330 Pair Map DDC 1 control DDC 1 mixer select DDC 1 gain select DDC 1 IF (intermediate frequency) mode DDC 1 complex to real enable Reserved DDC 1 decimation rate select 0x00 R/W |
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