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AD9694 Datasheet(PDF) 65 Page - Analog Devices |
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AD9694 Datasheet(HTML) 65 Page - Analog Devices |
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65 / 101 page  Data Sheet AD9694 Rev. 0 | Page 65 of 101 JESD204B BLOCK TEST MODES In addition to the ADC pipeline test modes, the AD9694 also has flexible test modes in the JESD204B block. These test modes are listed in Register 0x0573 and Register 0x0574. These test patterns can be injected at various points along the output data path. These test injection points are shown in Figure 82. Table 32 describes the various test modes available in the JESD204B block. For the AD9694, a transition from test modes (Register 0x0573 ≠ 0x00) to normal mode (Register 0x0573 = 0x00) requires an SPI soft reset. This is done by writing 0x81 to Register 0x0000 (self cleared). Transport Layer Sample Test Mode The transport layer samples are implemented in the AD9694 as defined by Section 5.1.6.3 in the JEDEC JESD204B specification. These tests are shown in Register 0x0571, Bit 5. The test pattern is equivalent to the raw samples from the ADC. Interface Test Modes The interface test modes are described in Register 0x0573, Bits[3:0]. These test modes are also explained in Table 32. The interface tests can be injected at various points along the data. See Figure 82 for more information on the test injection points. Register 0x0573, Bits[5:4] show where these tests are injected. Table 33, Table 34, and Table 35 show examples of some of the test modes when injected at the JESD204B sample input, physical layer (PHY) 10-bit input, and scrambler 8-bit input. In Table 32 through Table 35, UPx represents the user pattern control bits from the customer register map. Data Link Layer Test Modes The data link layer test modes are implemented in the AD9694 as defined by Section 5.3.3.8.2 in the JEDEC JESD204B specification. These tests are shown in Register 0x0574, Bits[2:0]. Test patterns inserted at the data link layer are useful for verifying the functionality of the data link layer. When the data link layer test modes are enabled, disable SYNCINB±x by writing 0xC0 to Register 0x0572. Table 32. JESD204B Interface Test Modes Output Test Mode Bit Sequence Pattern Name Expression Default 0000 Off (default) Not applicable Not applicable 0001 Alternating checker board 0x5555, 0xAAAA, 0x5555, … Not applicable 0010 1/0 word toggle 0x0000, 0xFFFF, 0x0000, … Not applicable 0011 31-bit PN sequence x31 + x28 + 1 0x0003AFFF 0100 23-bit PN sequence x23 + x18 + 1 0x003AFF 0101 15-bit PN sequence x15 + x14 + 1 0x03AF 0110 9-bit PN sequence x9 + x5 + 1 0x092 0111 7-bit PN sequence x7 + x6 + 1 0x07 1000 Ramp output (x) % 216 Ramp size depends on test injection point 1110 Continuous/repeat user test Register 0x0551 to Register 0x0558 User Pattern 1 to User Pattern 4, then repeat 1111 Single user test Register 0x0551 to Register 0x0558 User Pattern 1 to User Pattern 4, then zeros Table 33. JESD204B Sample Input for M = 2, S = 2, N' = 16 (Register 0x0573, Bits[5:4] = 'b00) Frame Number Converter Number Sample Number Alternating Checkerboard 1/0 Word Toggle Ramp 9-Bit PN 23-Bit PN User Repeat User Single 0 0 0 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 0 0 1 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 0 1 0 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 0 1 1 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 1 0 0 0xAAAA 0xFFFF (x +1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0] 1 0 1 0xAAAA 0xFFFF (x +1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0] 1 1 0 0xAAAA 0xFFFF (x +1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0] 1 1 1 0xAAAA 0xFFFF (x +1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0] 2 0 0 0x5555 0x0000 (x +2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0] 2 0 1 0x5555 0x0000 (x +2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0] 2 1 0 0x5555 0x0000 (x +2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0] 2 1 1 0x5555 0x0000 (x +2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0] 3 0 0 0xAAAA 0xFFFF (x +3) % 216 0x651A 0x3D72 UP4[15:0] UP4[15:0] 3 0 1 0xAAAA 0xFFFF (x +3) % 216 0x651A 0x3D72 UP4[15:0] UP4[15:0] |
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