DA9021 datasheet(48/142 Pages) DIALOG

48 / 142 page

DA9021/22

System PMIC with high efficiency USB power manager

Datasheet

Revision 2.5

17-Feb-2017

CFR0011-120-00 Rev 5

48 of 142

11.9 Power domain status (PWR_UP/GP_FB2)

The power domain status indicators are active high and assigned after the sequencer has processed

all IDs of a power domain (all assigned supplies are up). When domains are disabled during power

mode transitions the status indicator is released before the DA9021/22 sequencer processes the last

step of a domain.

PWR_UP is one mode of the general purpose indicator GP_FB2 that can also be used as a

configurable feedback signal that is level/time controlled from the power sequencer.

11.10 Supply rail fault (nVDD_FAULT)

nVDD_FAULT is an active low output signal to the host processor to indicate a VDDOUT low status.

The assertion of nVDD_FAULT indicates that the main battery and the supply input voltage is low

and therefore informs the host processor that the power will shut down very soon. After that the

processor may operate for a limited time from the backup battery, which can provide power to the

processor for a few cycles. In the event of nVDD_FAULT assertion the processor may be

programmed to enter an emergency mode, for example external memory data refresh is no longer

performed.

11.11 Interrupt request (nIRQ)

The nIRQ is an active low output signal which indicates that an interrupt causing event has occurred

and that the event and status information is available in the related registers. Such information can

be temperature and voltage of the PMIC, fault conditions, charging status, status changes at GPI

ports, and others. The event registers hold information about the events that have occurred. Events

are triggered by a status change at the monitored signals. When an event bit is set the nIRQ signal is

asserted (unless this interrupt is masked by a bit in the IRQ mask register). The nIRQ will not be

released until the event registers have been cleared.

11.12 Real time clock output (OUT_32K)

The OUT_32K is an output signal that generates a buffered signal of the DA9021/22 32 kHz

oscillator. The 32 kHz oscillator will always run on the DA9021/22 following the initial start-up from

NO-POWER mode until the device has reached NO-POWER mode again. The signal output buffer

can be disabled during POWERDOWN mode with bit OUT_32K_PD.

11.13 IO_supply voltage (VDD_IO)

VDD_IO is an independent IO supply rail input of DA9021/22 that can be assigned to the power

manager interface, power manager IOs and GPIOs. The rail assignment determines the IO voltage

levels and logic. The selection of the supply rail for GPIOs is also partially used for their alternate

functions. GPOs configured in open drain mode have to use the VDD_IO rail if an internal pull-up

resistor is required.

DA9021 Datasheet(PDF) 48 Page - Dialog Semiconductor